System and method for storing multibit data in non-volatile memory
View Patent ↗A method of reading a memory device having a plurality of memory cells by, and a device configured for, reading a first memory cell of the plurality of memory cells to generate a first read current, reading a second memory cell of the plurality of memory cells to generate a second read current, applying a first offset value to the second read current, and then combining the first and second read currents to form a third read current, and then determining a program state using the third read current. Alternately, a first voltage is generated from the first read current, a second voltage is generated from the second read current, whereby the offset value is applied to the second voltage, wherein the first and second voltages are combined to form a third voltage, and then the program state is determined using the third voltage.
1. A method of reading a memory device having a plurality of memory cells, comprising:
reading a first memory cell of the plurality of memory cells to generate a first read current;
reading a second memory cell of the plurality of memory cells to generate a second read current;
applying a first offset value to the second read current; then
combining the first read current and the second read current having the first offset value to form a third read current; and then
determining a program state using the third read current.
2. The method of claim 1 , wherein the combining comprises adding the first read current and the second read current having the first offset value together.
3. The method of claim 1 , further comprising:
reading a third memory cell of the plurality of memory cells to generate a fourth read current;
applying a second offset value to the fourth read current;
wherein the combining including combining the first read current, the second read current having the first offset value and the fourth read current having the second offset value to form the third read current.
4. The method of claim 3 , wherein the second offset value is different from the first offset value.
5. The method of claim 3 , wherein the combining comprises adding the first read current, the second read current having the first offset value and the fourth read current having the second offset value together.
6. The method of claim 1 , wherein the plurality of memory cells are arranged in an array of rows and columns of the memory cells, wherein each of the columns includes a bit line connected to the memory cells therein, wherein the first memory cell is disposed in a first one of the columns, and wherein the second memory cell is disposed in a second one of the columns different than the first one of the columns.
7. A method of reading a memory device having a plurality of memory cells, comprising:
reading a first memory cell of the plurality of memory cells to generate a first read current;
reading a second memory cell of the plurality of memory cells to generate a second read current;
generating a first voltage from the first read current;
generating a second voltage from the second read current;
applying a first offset value to the second voltage; then combining the first voltage and the second voltage having the first offset value to form a third voltage; and then
determining a program state using the third voltage.
8. The method of claim 7 , wherein the combining comprises adding the first voltage and the second voltage having the first offset value together.
9. The method of claim 7 , further comprising:
reading a third memory cell of the plurality of memory cells to generate a third read current;
generating a fourth voltage from the third read current;
applying a second offset value to the fourth voltage;
wherein the combining including combining the first voltage, the second voltage having the first offset value and the fourth voltage having the second offset value to form the third voltage.
10. The method of claim 9 , wherein the second offset value is different from the first offset value.
11. The method of claim 9 , wherein the combining comprises adding the first voltage, the second voltage having the first offset value and the fourth voltage having the second offset value together.
12. The method of claim 7 , wherein the plurality of memory cells are arranged in an array of rows and columns of the memory cells, wherein each of the columns includes a bit line connected to the memory cells therein, wherein the first memory cell is disposed in a first one of the columns, and wherein the second memory cell is disposed in a second one of the columns different than the first one of the columns.
13. A memory device, comprising: a semiconductor substrate;
a plurality of memory cells formed on the semiconductor substrate; and
circuitry formed on the semiconductor substrate and configured to:
read a first memory cell of the plurality of memory cells to generate a first read current;
read a second memory cell of the plurality of memory cells to generate a second read current;
apply a first offset value to the second read current; then
combine the first read current and the second read current having the first offset value to form a third read current; then
determine a program state using the third read current.
14. The device of claim 13 , wherein the combining comprises adding the first read current and the second read current having the first offset value together.
15. The device of claim 13 , wherein the circuitry is further configured to:
read a third memory cell of the plurality of memory cells to generate a fourth read current;
applying a second offset value to the fourth read current;
wherein the combining including combining the first read current, the second read current having the first offset value and the fourth read current having the second offset value to form the third read current.
16. The device of claim 15 , wherein the second offset value is different from the first offset value.
17. The device of claim 15 , wherein the combining comprises adding the first read current, the second read current having the first offset value and the fourth read current having the second offset value together.
18. The device of claim 13 , wherein:
the plurality of memory cells are arranged in an array of rows and columns of the memory cells;
each of the columns includes a bit line connected to the memory cells therein;
the first memory cell is disposed in a first one of the columns; and
the second memory cell is disposed in a second one of the columns different than the first one of the columns.
19. A memory device, comprising: a semiconductor substrate;
a plurality of memory cells formed on the semiconductor substrate; and
circuitry formed on the semiconductor substrate and configured to:
read a first memory cell of the plurality of memory cells to generate a first read current;
read a second memory cell of the plurality of memory cells to generate a second read current;
generate a first voltage from the first read current;
generate a second voltage from the second read current;
apply a first offset value to the second voltage; then
combine the first voltage and the second voltage having the first offset value to form a third voltage; then
determine a program state using the third voltage.
20. The device of claim 19 , wherein the combining comprises adding the first voltage and the second voltage having the first offset value together.
21. The device of claim 19 , wherein the circuitry is further configured to: read a third memory cell of the plurality of memory cells to generate a third read current;
generate a fourth voltage from the third read current;
apply a second offset value to the fourth voltage;
wherein the combining including combining the first voltage, the second voltage having the first offset value and the fourth voltage having the second offset value to form the third voltage.
22. The device of claim 21 , wherein the second offset value is different from the first offset value.
23. The device of claim 21 , wherein the combining comprises adding the first voltage, the second voltage having the first offset value and the fourth voltage having the second offset value together.
24. The device of claim 19 , wherein:
the plurality of memory cells are arranged in an array of rows and columns of the memory cells;
each of the columns includes a bit line connected to the memory cells therein;
the first memory cell is disposed in a first one of the columns; and
the second memory cell is disposed in a second one of the columns different than the first one of the columns.