Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network
Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. The embodiments are able to compensate for slope differences during both sub-threshold and linear operation of reference transistors.
1. A method of adjusting a reference transistor in a flash memory system, comprising:
receiving an input voltage;
multiplying the input voltage by a coefficient to generate an output voltage;
applying the output voltage to a gate of the reference transistor; and
using the reference transistor in a sense operation to determine a value stored in a selected memory cell.
2. The method of claim 1 , further comprising:
coupling the input voltage to gates of memory cells in a memory array.
3. The method of claim 1 , wherein the reference transistor operates in a sub-threshold region.
4. The method of claim 1 , wherein the reference transistor operates in a linear region.
5. The method of claim 2 , wherein the reference transistor operates in a sub-threshold region.
6. The method of claim 2 , wherein the reference transistor operates in linear region.
7. The method of claim 1 , wherein the input voltage is connected to a drain of the reference transistor.
8. The method of claim 7 , wherein an input current is connected to a drain of the reference transistor to produce the input voltage.
9. The method of claim 1 , wherein a slope of a current-voltage characteristic curve of the reference transistor and a slope of a current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.
10. The method of claim 1 , wherein the input voltage is coupled to a normalizing circuit.
11. The method of claim 10 , wherein an output of the normalizing circuit is connected to the selected memory cell.
12. The method of claim 10 , wherein the normalizing circuit is a current mirror circuit.
13. The method of claim 10 , wherein the value from the memory cells are bitline current or sourceline current.
14. The method of claim 1 , wherein the memory cells are non-volatile.
15. The method of claim 1 , wherein the multiplying is performed by a driver circuit coupled to the gate of the reference transistor.
16. The method of claim 1 , wherein the multiplying is performed by a pair of input capacitors coupled to the gate of the reference transistor.
17. The method of claim 1 , wherein the multiplying is performed by a pair of operational amplifiers coupled to the gate of the reference transistor.
18. A method of adjusting a characteristic curve of a reference memory cell in a flash memory system, comprising:
receiving an input voltage;
multiplying the input voltage by a coefficient to generate an output voltage;
applying the output voltage to a gate of the reference memory cell; and
using the reference memory cell in a sense operation to determine a value stored in a selected memory cell.
19. The method of claim 18 , wherein a slope of a current-voltage characteristic curve of the reference memory cell and a slope of a current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.
20. The method of claim 19 , wherein the reference memory cell operates in a sub-threshold region.
21. The method of claim 19 , wherein the reference memory cell operates in a linear region.
22. The method of claim 18 , wherein the reference memory cell operates in sub-threshold regions.
23. The method of claim 18 , wherein the reference memory cell operates in a linear region.
24. The method of claim 18 , wherein the input voltage is connected to a drain of the reference memory cell.
25. The method of claim 18 , wherein the reference memory cell is non-volatile.
26. The method of claim 18 , wherein the multiplying is performed by a driver circuit coupled to the gate of the reference memory cell.
27. The method of claim 18 , wherein the multiplying is performed by a pair of input capacitors coupled to the gate of the reference memory cell.
28. The method of claim 18 , wherein the multiplying is performed by a pair of operational amplifiers coupled to the gate of the reference memory cell.