Vertically stacked nanosheet CMOS transistor
View Patent ↗Embodiments of the present invention are directed to techniques for generating vertically stacked nanosheet CMOS (Complementary Metal Oxide Semiconductor) transistor architectures. In a non-limiting embodiment of the invention, a first rare earth oxide layer is formed over a substrate. An n-FET nanosheet stack is formed on the rare earth oxide layer. The n-FET nanosheet stack includes a first nanosheet. A second rare earth oxide layer is formed on the n-FET nanosheet stack. A p-FET nanosheet stack is formed on the second rare earth oxide layer. The p-FET nanosheet stack includes a second nanosheet.
1. A method for forming a semiconductor device, the method comprising:
forming a first rare earth oxide layer on a substrate;
forming a first nanosheet stack on the rare earth oxide layer, the first nanosheet stack comprising a first nanosheet;
forming a second rare earth oxide layer on the first nanosheet stack; and
forming a second nanosheet stack on the second rare earth oxide layer, the second nanosheet stack comprising a second nanosheet.
2. The method of claim 1 further comprising forming a first source and a first drain on the first rare earth oxide layer such that the first source is adjacent to a first sidewall of the first nanosheet and the first drain is adjacent to a second sidewall of the first nanosheet, the first and second sidewalls on opposite ends of the first nanosheet.
3. The method of claim 2 further comprising forming a dielectric layer on the first source and first drain.
4. The method of claim 3 further comprising forming a second source and a second drain on the dielectric layer such that the second source is adjacent to a first sidewall of the second nanosheet and the second drain is adjacent to a second sidewall of the second nanosheet, the first and second sidewalls on opposite ends of the second nanosheet.
5. The method of claim 4 further comprising:
doping the first source and the first drain with a first dopant; and
doping the second source and the second drain with a second dopant.
6. The method of claim 5 , wherein the first dopant is an n-type dopant and the second dopant is a p-type dopant.
7. The method of claim 5 , wherein the first dopant is a p-type dopant and the second dopant is an n-type dopant.
8. The method of claim 4 , wherein:
the first source and the first drain comprise phosphorus doped silicon; and
the second source and the second drain comprise boron doped silicon germanium.
9. The method of claim 2 further comprising epitaxially growing the first source and the first drain on exposed surfaces of the first rare earth oxide layer and on exposed surfaces of the first nanosheet.
10. The method of claim 1 , wherein a thickness of the second rare earth oxide layer is greater than a thickness of the first nanosheet.
11. The method of claim 1 , wherein the first nanosheet stack further comprises a third nanosheet vertically stacked over the first nanosheet and the second nanosheet stack further comprises a fourth nanosheet vertically stacked over the second nanosheet.
12. A method for forming a semiconductor device, the method comprising:
forming a first rare earth oxide layer on a substrate;
forming an n-FET nanosheet stack on the rare earth oxide layer, the n-FET nanosheet stack comprising vertically stacked silicon nanosheets;
forming a second rare earth oxide layer on the n-FET nanosheet stack; and
forming a p-FET nanosheet stack on the second rare earth oxide layer, the p-FET nanosheet stack comprising vertically stacked silicon nanosheets.
13. The method of claim 12 further comprising forming a first source and a first drain on the first rare earth oxide layer such that the first source is adjacent to a first sidewall of the n-FET nanosheet stack and the first drain is adjacent to a second sidewall of the n-FET nanosheet stack, the first and second sidewalls on opposite ends of the n-FET nanosheet stack.
14. The method of claim 13 further comprising forming a dielectric layer on the first source and first drain.
15. The method of claim 14 further comprising forming a second source and a second drain on the dielectric layer such that the second source is adjacent to a first sidewall of the p-FET nanosheet stack and the second drain is adjacent to a second sidewall of the p-FET nanosheet stack, the first and second sidewalls on opposite ends of the p-FET nanosheet stack.