Integrated circuit (IC) device including a force mitigation system for reducing under-pad damage caused by wire bond
An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.
1. A silicon die, comprising:
a substrate;
one or more wire bond regions, each wire bond region comprising:
a metal region located above the substrate;
a force mitigation layer located above the metal region;
a plurality of voids defined in the force mitigation layer;
a sealing layer above the force mitigation layer and configured to seal the plurality of voids to define a plurality of sealed voids in the force mitigation layer;
a wire bond pad formed over the sealing layer; and
one or more semiconductor devices formed in a region of the die below the force mitigation layer and metal region.
2. The silicon die of claim 1 , wherein the force mitigation layer and the sealing layer are formed from non-metal materials.
3. The silicon die of claim 1 , wherein the force mitigation layer comprises an oxide dielectric layer, wherein the plurality of sealed voids are formed in the oxide dielectric layer.
4. The silicon die of claim 3 , wherein the plurality of sealed voids comprise a plurality of vias formed in the oxide dielectric layer.
5. The silicon die of claim 1 , further comprising a passivation layer formed over the sealing layer.
6. The silicon die of claim 1 , wherein the plurality of sealed voids defined in the force mitigation layer comprises a two-dimensional array of sealed voids.
7. The silicon die of claim 1 , wherein the plurality of sealed voids defined in the force mitigation layer maintain a partial vacuum in each sealed void.
8. The silicon die of claim 1 , wherein each of the sealed voids has a lateral width that gradually reduces in a tapered manner toward a top end of the sealed void.
9. The silicon die of claim 1 , wherein the force mitigation layer comprises an oxide dielectric layer, wherein the plurality of sealed voids are formed in the oxide dielectric layer.
10. A silicon die, comprising:
a substrate;
a wire bond pad;
one or more semiconductor devices formed below the wire bond pad; and
a force mitigation system located below the wire bond pad and above the one or more semiconductor devices, the force mitigation system including:
a metal shock plate region; and
a force mitigation layer above the metal shock plate region, the force mitigation layer including a plurality of sealed voids defined in a non-metal region, wherein the plurality of sealed voids are sealed on a top side by a non-metal sealing layer located above the force mitigation layer.
11. An electronic device, comprising:
a silicon die comprising:
a die substrate;
one or more wire bond regions, each wire bond region comprising:
a metal region located above the substrate;
a sealing layer located above the non-metal layer;
a force mitigation layer located between the metal region and the sealing layer;
a plurality of sealed voids defined in the force mitigation layer; and
a wire bond pad formed over the sealing layer; and
one or more semiconductor devices formed in a region of the die below the force mitigation layer and metal region;
one or more conductive leads; and
one or more wires, each wire having a first end bonded to a respective wire bond pad on the silicon die and a second end bonded to a respective lead.