Twin bit non-volatile memory cells with floating gates in substrate trenches
A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.
1. A twin bit memory cell, comprising:
a semiconductor substrate having an upper surface;
first and second trenches formed into the upper surface and spaced apart from each other;
a first floating gate of conductive material disposed in the first trench and insulated from the substrate;
a second floating gate of conductive material disposed in the second trench and insulated from the substrate;
a first erase gate of conductive material disposed over and insulated from the first floating gate;
a second erase gate of conductive material disposed over and insulated from the second floating gate;
a word line gate of conductive material disposed over and insulated from a portion of the upper surface that is between the first and second trenches;
a first source region formed in the substrate under the first trench;
a second source region formed in the substrate under the second trench;
wherein a continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.
2. The twin bit memory cell of claim 1 , wherein the first trench only contains therein the first floating gate and insulation material that insulates the first floating gate from the substrate, and wherein the second trench only contains therein the second floating gate and insulation material that insulates the second floating gate from the substrate.
3. A twin bit memory cell, comprising:
a semiconductor substrate having an upper surface;
first and second trenches formed into the upper surface and spaced apart from each other;
a first floating gate of conductive material disposed in the first trench and insulated from the substrate;
a second floating gate of conductive material disposed in the second trench and insulated from the substrate;
a first erase gate of conductive material disposed over and insulated from the first floating gate;
a second erase gate of conductive material disposed over and insulated from the second floating gate;
a word line gate of conductive material disposed over and insulated from a portion of the upper surface that is between the first and second trenches;
a first source region formed at the upper surface of the substrate adjacent the first trench;
a second source region formed at the upper surface of the substrate adjacent the second trench;
wherein a continuous channel region of the substrate extends from the first source region, along a first side wall of the first trench, along a bottom wall of the first trench, along a second side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a first side wall of the second trench, along a bottom wall of the second trench, along a second side wall of the second trench and to the second source region.
4. The twin bit memory cell of claim 3 , wherein the first trench only contains therein the first floating gate and insulation material that insulates the first floating gate from the substrate, and wherein the second trench only contains therein the second floating gate and insulation material that insulates the second floating gate from the substrate.
5. A twin bit memory cell, comprising:
a semiconductor substrate having an upper surface;
first and second trenches formed into the upper surface and spaced apart from each other;
first and second floating gates of conductive material disposed in the first trench spaced apart from each other and insulated from the substrate;
third and fourth floating gates of conductive material disposed in the second trench spaced apart from each other and insulated from the substrate;
a first erase gate of conductive material disposed over and insulated from the first and second floating gates;
a second erase gate of conductive material disposed over and insulated from the third and fourth floating gates;
a word line gate of conductive material disposed over and insulated from a portion of the upper surface that is between the first and second trenches;
a first source region formed in the substrate under the first trench;
a second source region formed in the substrate under the second trench;
a first control gate of conductive material disposed in the first trench, and between and insulated from the first and second floating gates;
a second control gate of conductive material disposed in the second trench, and between and insulated from the third and fourth floating gates;
wherein a continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.
6. The twin bit memory cell of claim 5 , wherein the first erase gate has a first portion that is disposed between the first and second floating gates, and a second portion that extends up and over the first and second floating gates, such that the first erase gate wraps around an edge of the first floating gate and wraps around an edge of the second floating gate; and
wherein the second erase gate has a first portion that is disposed between the third and fourth floating gates, and a second portion that extends up and over the third and fourth floating gates, such that the second erase gate wraps around an edge of the third floating gate and wraps around an edge of the fourth floating gate.
7. A method of forming a twin bit memory cell, comprising:
forming first and second trenches into an upper surface of a semiconductor substrate, wherein the first and second trenches are spaced apart from each other;
forming a first floating gate of conductive material in the first trench and insulated from the substrate;
forming a second floating gate of conductive material in the second trench and insulated from the substrate;
forming a first erase gate of conductive material over and insulated from the first floating gate;
forming a second erase gate of conductive material over and insulated from the second floating gate;
forming a word line gate of conductive material over and insulated from a portion of the upper surface that is between the first and second trenches;
forming a first source region in the substrate under the first trench;
forming a second source region in the substrate under the second trench;
wherein a continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.
8. The method of claim 7 , wherein the first trench only contains therein the first floating gate and insulation material that insulates the first floating gate from the substrate, and wherein the second trench only contains therein the second floating gate and insulation material that insulates the second floating gate from the substrate.
9. A method of forming a twin bit memory cell, comprising:
forming first and second trenches into an upper surface of a semiconductor substrate, wherein the first and second trenches are spaced apart from each other;
forming a first floating gate of conductive material in the first trench and insulated from the substrate;
forming a second floating gate of conductive material in the second trench and insulated from the substrate;
forming a first erase gate of conductive material over and insulated from the first floating gate;
forming a second erase gate of conductive material over and insulated from the second floating gate;
forming a word line gate of conductive material over and insulated from a portion of the upper surface that is between the first and second trenches;
forming a first source region at the upper surface of the substrate adjacent the first trench;
forming a second source region at the upper surface of the substrate adjacent the second trench;
wherein a continuous channel region of the substrate extends from the first source region, along a first side wall of the first trench, along a bottom wall of the first trench, along a second side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a first side wall of the second trench, along a bottom wall of the second trench, along a second side wall of the second trench and to the second source region.
10. The method of claim 9 , wherein the first trench only contains therein the first floating gate and insulation material that insulates the first floating gate from the substrate, and wherein the second trench only contains therein the second floating gate and insulation material that insulates the second floating gate from the substrate.
11. A method of forming a twin bit memory cell, comprising:
forming first and second trenches into an upper surface of a semiconductor substrate, wherein the first and second trenches are spaced apart from each other;
forming first and second floating gates of conductive material in the first trench spaced apart from each other and insulated from the substrate;
forming third and fourth floating gates of conductive material in the second trench spaced apart from each other and insulated from the substrate;
forming a first erase gate of conductive material over and insulated from the first and second floating gates;
forming a second erase gate of conductive material over and insulated from the third and fourth floating gates;
forming a word line gate of conductive material over and insulated from a portion of the upper surface that is between the first and second trenches;
forming a first source region in the substrate under the first trench;
forming a second source region in the substrate under the second trench;
forming a first control gate of conductive material in the first trench, and between and insulated from the first and second floating gates;
forming a second control gate of conductive material in the second trench, and between and insulated from the third and fourth floating gates;
wherein a continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.
12. The method of claim 11 , wherein the first erase gate has a first portion that is disposed between the first and second floating gates, and a second portion that extends up and over the first and second floating gates, such that the first erase gate wraps around an edge of the first floating gate and wraps around an edge of the second floating gate; and
wherein the second erase gate has a first portion that is disposed between the third and fourth floating gates, and a second portion that extends up and over the third and fourth floating gates, such that the second erase gate wraps around an edge of the third floating gate and wraps around an edge of the fourth floating gate.