Method and apparatus for enabling wide input common-mode range in SAR ADCS with no additional active circuitry
View Patent ↗A differential successive approximation register (SAR) analog-to-digital converter (ADC) with wide input common-mode range adds one step to its conversion process. No additional circuitry is required for full rail-to-rail common mode voltage operation. In a first step the top-plate nodes vcp and vcn may be reset to a fixed voltage vcm. Then in a next step sampling may be performed while leaving vcp and vcn floating but shorted. Whereby a single node vx is formed, which provides for simple capacitive voltage division. Thereafter a standard sequential SAR bit-by-bit analog-to-digital conversion is performed. the voltage at node vx will follow vcmin during the entire sampling phase, with a limitation in rate of change only limited by the RC time constant of the shorting switch and the sampling capacitors. This will have much higher bandwidth than any active OTA-based tracking circuit.
1. A method for providing wide input common-mode range in a successive approximation register (SAR) analog-to-digital convertor (ADC), said method comprising the steps of:
resetting top plate nodes vcp and vcn of a plurality of binary weighted capacitors to a voltage vcm;
sampling differential voltages Vinp and Vinn on bottom plate nodes vcp and vcn, respectively, while coupling the top plate nodes vcp and vcn together and floating; and
performing a sequential SAR analog-to-digital conversion on the sampled differential voltages Vinp and Vinn.
2. The method according to claim 1 , wherein the SAR ADC is a differential input SAR ADC.
3. The method according to claim 1 , wherein the SAR ADC is fabricated in integrated circuit device.
4. The method according to claim 3 , wherein the integrated circuit device is a microcontroller.
5. A method for providing wide input common-mode range in a successive approximation register (SAR) analog-to-digital convertor (ADC), said method comprising the steps of:
coupling top plates of a first half of a plurality of binary weighted capacitors to a first input of a voltage comparator and coupling top plates of a second half of the plurality of binary weighted capacitors to a second input of the voltage comparator;
coupling a top plate of a first dummy capacitor to the first input of the voltage comparator and coupling a top plate of a second dummy capacitor to the second input of the voltage comparator;
coupling a previous first reference voltage to bottom plates of the first half of the plurality of binary weighted capacitors;
coupling a previous second reference voltage to bottom plates of the second half of the plurality of binary weighted capacitors;
coupling a third reference voltage to the top plates of the plurality of binary weighted capacitors, and to the top and bottom plates of the first and second dummy capacitors;
decoupling the bottom plates of the plurality of binary weighted capacitors from the previous first and second reference voltages;
coupling the bottom plates of the first half of the plurality of binary weighted capacitors and the bottom plate of the first dummy capacitor to a positive input voltage, Vinp;
coupling the bottom plates of the second half of the plurality of binary weighted capacitors and the bottom plate of the second dummy capacitor to a negative input voltage, Vinn;
coupling the top plates of the plurality of binary weighted capacitors and the first and second dummy capacitors together;
decoupling the top plates of the first half of the plurality of binary weighted capacitors and the first dummy capacitor from the top plates of the second half of the plurality of binary weighted capacitors and the second dummy capacitor;
coupling the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors to the third reference voltage;
determining whether a first voltage on the first input of the voltage comparator is greater than a second voltage on the second input thereof;
wherein
if the first voltage is greater than the second voltage then provide a first logic level output from the voltage comparator, and
if the first voltage is less than the second voltage then provide a second logic level output from the voltage comparator; and
continue doing a successive approximation analog-to-digital conversion until finished with the conversion.
6. The method according to claim 5 , wherein the previous first reference voltage is from a first digital-to-analog converter (DAC), and the previous second reference voltage is from a second DAC.
7. The method according to claim 6 , wherein the previous first and second reference voltages are Vref, and the third reference voltage is Vref/2.
8. The method according to claim 5 , wherein the first logic level is a logic high or logic “1”, and the second logic level is a logic low or logic “0”.
9. The method according to claim 5 , wherein the SAR ADC is a differential input SAR ADC.
10. The method according to claim 5 , wherein the SAR ADC is fabricated in integrated circuit device.
11. The method according to claim 10 , wherein the integrated circuit device is a microcontroller.
12. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising circuitry configured to:
couple a third reference voltage to top plates of a plurality of binary weighted capacitors and top and bottom plates of first and second dummy capacitors;
couple a previous first reference voltage to bottom plates of a first half of the plurality of binary weighted capacitors;
couple a previous second reference voltage to bottom plates of a second half of the plurality of binary weighted capacitors;
decouple the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors from the respective first, second and third reference voltages;
couple together the bottom plates of the plurality of binary weighted capacitors and the first and second dummy capacitors;
couple a positive input voltage, Vinp, to the bottom plates of the first half of the plurality of binary weighted capacitors and the first dummy capacitor;
couple a negative input voltage, Vinn, to the bottom plates of the second half of the plurality of binary weighted capacitors and the second dummy capacitor;
decouple the bottom plates of the first half of the plurality of binary weighted capacitors and the first dummy capacitor from the bottom plates of the second half of the plurality of binary weighted capacitors and the second dummy capacitor;
compare a voltage Vx at the top plates of the first half of the plurality of binary weighted capacitors and the first dummy capacitor with a voltage Vy at the top plates of the second half of the plurality of binary weighted capacitors and the second dummy capacitor;
wherein
if the voltage Vx is greater than the voltage Vy then
couple a fourth voltage to the bottom plate of a most significant bit (MSB) one of the first half of the plurality of binary weighted capacitors,
couple a fifth voltage to the bottom plate of a MSB one of the second half of the plurality of binary weighted capacitors, and
couple the third voltage to the bottom plates of the remaining plurality of binary weighted capacitors and the first and second dummy capacitors, or
if the voltage Vx is less than the voltage Vy then
couple the fifth voltage to the bottom plate of the MSB one of the first half of the plurality of binary weighted capacitors,
couple the fourth voltage to the bottom plate of the MSB one of the second half of the plurality of binary weighted capacitors, and
couple the third voltage to the bottom plates of the remaining plurality of binary weighted capacitors and the first and second dummy capacitors; and
continue doing a successive approximation analog-to-digital conversion until finished with the conversion.
13. The SAR ADC according to claim 12 , wherein
the first previous reference voltage is from a first digital-to-analog converter;
the second previous reference voltage is from a second digital-to-analog converter;
the third reference voltage is Vref/2;
the fourth reference voltage is zero volts; and
the fifth reference voltage is Vref.
14. The SAR ADC according to claim 12 , wherein the successive approximation register (SAR) analog-to-digital converter (ADC) is a differential input SAR ADC.
15. The SAR ADC according to claim 12 , wherein the SAR ADC is fabricated in integrated circuit device.
16. The SAR ADC according to claim 15 , wherein the integrated circuit device is a microcontroller.