Granted Patent B2

US 10,581,443 · App. 16/173,289 · Granted Mar 3, 2020

Inventors: Anders Vinje (Trondheim, NO); Ivar Løkken (Trondheim, NO)

Assignee: Microchip Technology Incorporated

H03M1/0607H03M1/1023H03M1/468

Abstract

Claims (84)

1. A method for offset correction in a successive approximation register (SAR) analog-to-digital converter (ADC) using a reduced capacitor array digital-to-analog converter (DAC), said method comprising the steps of:

coupling together positive and negative inputs of a SAR ADC;

determining a digital representation of an offset voltage of the SAR DAC;

storing the digital representation of the offset voltage in an offset register;

configuring a reduced capacitor array DAC, comprising a plurality of offset correction capacitors, with the stored digital representation of the input offset voltage to provide an offset correction voltage;

decoupling the positive and negative inputs of the SAR ADC;

coupling a differential voltage to the positive and negative inputs of the SAR ADC; and

performing a SAR conversion of the differential voltage while coupling with the offset correction voltage from the reduced capacitor array DAC.

2. The method according to claim 1 , wherein the plurality of offset correction capacitors are coupled to a plurality of reference voltages selected by the digital representation of the offset voltage stored in the offset register.

3. The method according to claim 2 , wherein the plurality of reference voltages are binary weighted from Vrefp to Vrefn voltages.

4. The method according to claim 3 , wherein a common mode voltage Vcm is about equal to (Vrefp+Vrefn)/2.

5. The method according to claim 3 , wherein the plurality of reference voltages are provided from a series connected resistive voltage divider string coupled between Vrefp and Vrefn.

6. The method according to claim 1 , wherein the plurality of offset correction capacitors comprises N positive offset correction capacitors having top plates coupled together and forming a node Vx, and N negative offset correction capacitors having top plates coupled together and forming a node Vy, where N is the number of offset voltage correction bits of the reduced capacitor array DAC.

7. The method according to claim 6 , wherein N is equal to five (5) and further comprising the steps of:

coupling a bottom plate of a first positive offset correction capacitor selectably to Vcm, Vrefp/2 or Vrefn/2;

coupling a bottom plate of a first negative offset correction capacitor selectably to Vcm, Vrefn/2 or Vrefp/2;

coupling a bottom plate of a second positive offset correction capacitor selectably to Vcm, Vrefp/4 or Vrefn/4;

coupling a bottom plate of a second negative offset correction capacitor selectably to Vcm, Vrefn/4 or Vrefp/4;

coupling a bottom plate of a third positive offset correction capacitor selectably to Vcm, Vrefp/8 or Vrefn/8;

coupling a bottom plate of a third negative offset correction capacitor selectably to Vcm, Vrefn/8 or Vrefp/8;

coupling a bottom plate of a fourth positive offset correction capacitor selectably to Vcm, Vrefp/16 or Vrefn/16;

coupling a bottom plate of a fourth negative offset correction capacitor selectably to Vcm, Vrefn/16 or Vrefp/16;

coupling a bottom plate of a fifth positive offset correction capacitor selectably to Vcm, Vrefp/32 or Vrefn/32; and

coupling a bottom plate of a fifth negative offset correction capacitor selectably to Vcm, Vrefn/32 or Vrefp/32, whereby the offset compensation voltage is created.

8. The method according to claim 6 , wherein N is equal to six (6) and further comprising the steps of:

coupling a top plate of a sixth positive offset correction capacitor to the node Vx;

coupling a top plate of a sixth negative offset correction capacitor to the node Vy;

coupling a bottom plate of the sixth positive offset correction capacitor selectably to Vcm, Vrefp or Vrefn; and

coupling a bottom plate of the sixth negative offset correction capacitor selectably to Vcm, Vrefn or Vrefp, whereby the voltage offset correction range is doubled.

9. The method according to claim 1 , further comprising the step of coupling the bottom plates of the positive and negative offset correction capacitors to the common mode voltage Vcm during a sampling phase of the SAR ADC.

10. The method according to claim 1 , further comprising the step of disabling the offset compensation voltage.

11. The method according to claim 1 , further comprising the step of doing offset correction upon start-up.

12. The method according to claim 1 , further comprising the step of doing offset correction periodically.

13. The method according to claim 1 , wherein the SAR ADC is a differential input SAR ADC.

14. A method for correcting for an offset voltage in an analog-to-digital converter (ADC), comprising the steps of:

coupling together inputs of an ADC to create an offset voltage;

converting the offset voltage into a digital representation thereof;

storing the digital representation of the offset voltage in an offset register;

deriving an offset compensation voltage from the stored digital representation of the offset voltage stored in the offset register;

receiving an input analog voltage;

correcting for the offset voltage by scaling voltage of a least-significant-bit; and

converting the input analog voltage to a digital output value;

wherein the SAR ADC is a differential input SAR ADC.

15. An analog-to-digital converter (ADC), comprising circuitry configured to:

couple together inputs of an ADC to create an offset voltage;

convert the offset voltage into a digital representation thereof;

store the digital representation of the offset voltage in an offset register;

derive an offset compensation voltage from the stored digital representation of the offset voltage in the offset register;

receive an analog voltage;

convert the analog voltage to a digital value; and

correct for the offset voltage by scaling reference voltages to a reduced capacitor array digital-to-analog converter (DAC) associated with a least-significant-bit of the ADC.

16. The ADC according to claim 15 , wherein the ADC is part of a microcontroller integrated circuit.

17. An apparatus for offset correction in a successive approximation register (SAR) analog-to-digital converter (ADC) using a reduced capacitor array digital-to-analog converter (DAC), said apparatus comprising:

a SAR ADC comprising:

inputs for a positive voltage Vinp and a negative voltage Vinn,

a positive reference voltage Vrefp and a negative reference voltage Vrefn, and

a common mode voltage Vcm;

a first plurality of binary weighted capacitors having top plates coupled together to form a node Vx;

a second plurality of binary weighted capacitors having top plates coupled together to form a node Vy;

a plurality of first switches adapted for selectably coupling the bottom plates of the first plurality of binary weighted capacitors to voltages Vrefp, Vrefn, Vcm, and Vinp;

a plurality of second switches adapted for selectably coupling the bottom plates of the second plurality of binary weighted capacitors to the voltages Vrefp, Vrefn, Vcm, and Vinn;

a reduced capacitor array DAC comprising:

N positive offset correction capacitors having top plates coupled to the node Vx,

N negative offset correction capacitors having top plates coupled to the node Vy,

a plurality of third switches adapted for selectably coupling bottom plates of the N positive offset correction capacitors to Vcm and a plurality of scaled voltage references Vrefp/2 m and Vrefn/2 m , where m is a positive integer; and

a plurality of fourth switches adapted for selectably coupling bottom plates of the N negative offset correction capacitors to Vcm and the plurality of scaled voltage references Vrefn/2 m and Vrefp/2 m , where m is a positive integer.

18. The apparatus according to claim 17 , wherein N is equal to five (5) and comprises:

the bottom plate of a first positive offset correction capacitor is selectably coupled to Vcm, Vrefp/2 or Vrefn/2;

the bottom plate of a first negative offset correction capacitor is selectably coupled to Vcm, Vrefn/2 or Vrefp/2;

the bottom plate of a second positive offset correction capacitor is selectably coupled to Vcm, Vrefp/4 or Vrefn/4;

the bottom plate of a second negative offset correction capacitor is selectably coupled to Vcm, Vrefn/4 or Vrefp/4;

the bottom plate of a third positive offset correction capacitor is selectably coupled to Vcm, Vrefp/8 or Vrefn/8;

the bottom plate of a third negative offset correction capacitor is selectably coupled to Vcm, Vrefn/8 or Vrefp/8;

the bottom plate of a fourth positive offset correction capacitor is selectably coupled to Vcm, Vrefp/16 or Vrefn/16;

the bottom plate of a fourth negative offset correction capacitor is selectably coupled to Vcm, Vrefn/16 or Vrefp/16;

the bottom plate of a fifth positive offset correction capacitor is selectably coupled to Vcm, Vrefp/32 or Vrefn/32; and

the bottom plate of a fifth negative offset correction capacitor is selectably coupled to Vcm, Vrefn/32 or Vrefp/32, whereby the offset compensation voltage is created.

19. The apparatus according to claim 18 , wherein N is equal to six (6) and further comprises:

the top plate of a sixth positive offset correction capacitor is coupled to the node Vx;

the top plate of a sixth negative offset correction capacitor is coupled to the node Vy,

the bottom plate of the sixth positive offset correction capacitor is selectably coupled to Vcm, Vrefp or Vrefn; and

the bottom plate of the sixth negative offset correction capacitor is selectably coupled to Vcm, Vrefn or Vrefp;

whereby the voltage offset correction range is doubled.

20. The method according to claim 17 , wherein the SAR ADC is a differential input SAR ADC.

Assignments (13)

Cited By (1)

US 12,562,747