IC taps with control register and scan router coupling taps
A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
1. An integrated circuit comprising:
a first circuit block including a first TAP, the first TAP having a first test clock input, a first test mode select input, a first test data input, and a first test data output;
a second circuit block including a second TAP, the second TAP having a second test clock input, a second test mode select input, a second test data input, and a second test data output;
a register having control outputs: and
a scan router having control inputs coupled to the control outputs, a scan in input, a scan out output, a first scan in output coupled to the first test data input, a first scan out input coupled to the first test data output, a second scan in output coupled to the second test data input, and a second scan out input coupled to the second test data output.
2. The integrated circuit of claim 1 in which the scan router includes a first multiplexor having a control input coupled to one of the control inputs, first input coupled to the scan in input and the first scan in output, a second input coupled to the first scanout input, and an output coupled to the second scan in output.
3. The integrated circuit of claim 2 in which the scan router includes a second multiplexor having a control input coupled to one of the control inputs, first input coupled to the first scan out input, a second input coupled to the second scan out input, and an output coupled to the scan out output.
4. The integrated circuit of claim 1 in which the, the scan router includes multiplexer circuitry coupled to the control inputs and selectively:
(i) coupling the scan in input to the first scan in output and couple the scan out output to the first scan out input;
(ii) coupling the scan in input to the second scan in output and couple the scan out output to the second scan out input; and
(iii) coupling the scan in input to the first scan in output, couple the first scan out input to the second scan in output, and couple the scan out output to the second scan out input.
5. The integrated circuit of claim 1 including a test access mechanism controller that includes the register.