Method of forming barrier free contact for metal interconnects

1. A method for fabricating a semiconductor device, comprising:

forming a first insulating layer having one or more vias formed in at least a portion of the first insulating layer, wherein the one or more vias are filled with a first metallic material;

forming a cap layer on a top surface of the first insulating layer and a top surface of the one or more vias formed in at least a portion of the first insulating layer;

forming a second insulating layer on a top surface of the cap layer;

forming a sacrificial dielectric layer on the second insulating layer;

forming a dual damascene structure having a trench in an upper portion and vias extending from the trench in a lower portion of the sacrificial dielectric layer, the second insulating layer and the cap layer and exposing at least a portion of a top surface of the first metallic material in the vias;

forming a self-assembled monolayer of a material on the exposed top surface of the first metallic material in the vias;

forming a metal-containing barrier layer on an exposed surface of the dual damascene structure and a portion of the self-assembled monolayer to expose a top surface of the self-assembled monolayer;

removing the self-assembled monolayer to expose the top surface of the first metallic material in the vias; and

filling the vias and the trench with a second metallic material, wherein the second metallic material is in contact with the first metallic material;

wherein the semiconductor device is formed as part of a back-end-of-line (BEOL) structure or as part of a middle-of-line (MOL) structure.

2. The method according to claim 1 , wherein the first insulating layer comprises a low-k dielectric material.

3. The method according to claim 1 , wherein the vias in the first insulating layer further comprise another barrier layer formed on sidewalls of the vias and an exposed surface of the first insulating layer.

4. The method according to claim 3 , wherein the other barrier layer comprises one or more of titanium nitride, tantalum nitride and ruthenium.

5. The method according to claim 1 , wherein the first metallic material is selected from the group consisting of aluminum, tungsten, copper and cobalt.

6. The method according to claim 1 , wherein the self-assembled monolayer comprises one or more of a thiol group, a phosphonic acid group and a phosphonate group.

7. The method according to claim 1 , wherein the step of removing the self-assembled monolayer comprises a plasma etch using N 2 /H 2 chemistry.

8. The method according to claim 1 , wherein the first insulating layer and the second insulating layer independently comprises an ultra low-k dielectric material.

9. The method according to claim 1 , wherein the first metallic material and the second metallic material are the same metallic material.

10. The method according to claim 1 , wherein the first metallic material and the second metallic material are copper.

11. The method according to claim 1 , wherein the first metallic material and the second metallic material are cobalt.

12. A semiconductor structure comprising:

a first insulating layer having one or more vias in at least a portion of the first insulating layer, wherein the one or more vias contain a first metallic material;

a cap layer disposed on a top surface of the first insulating layer and a top surface of the one or more vias;

a second insulating layer disposed on a top surface of the cap layer;

a sacrificial dielectric layer disposed on the second insulating layer;

a dual damascene structure having a trench in an upper portion and vias extending from the trench in a lower portion of the sacrificial dielectric layer, the second insulating layer and the cap layer and configured to expose at least a portion of a top surface of the first metallic material in the one or more vias;

a self-assembled monolayer of a material disposed on an exposed top surface of the first metallic material in the vias;

a metal-containing barrier layer disposed on an exposed surface of the dual damascene structure and a portion of the self-assembled monolayer and configured to expose a top surface of the self-assembled monolayer; and

a second metallic material disposed in and filling the vias and the trench, wherein the second metallic material is in contact with the first metallic material;

wherein the semiconductor structure comprises one of a BEOL structure or a MOL structure.

13. The semiconductor structure according to claim 12 , wherein the first metallic material is selected from the group consisting of aluminum, tungsten, copper and cobalt.

14. The semiconductor structure according to claim 12 , wherein the self-assembled monolayer comprises one or more of a thiol group, a phosphonic acid group and a phosphonate group.

15. The semiconductor structure according to claim 12 , wherein the first insulating layer and the second insulating layer independently comprises an ultra low-k dielectric material.

16. The semiconductor structure according to claim 12 , wherein the first metallic material and the second metallic material are the same metallic material.

17. The semiconductor structure according to claim 12 , wherein the vias in the first insulating layer further comprise another barrier layer formed on sidewalls of the vias and an exposed surface of the first insulating layer.

18. The semiconductor structure according to claim 17 , wherein the other barrier layer comprises one or more of titanium nitride, tantalum nitride and ruthenium.

19. The semiconductor structure according to claim 12 , wherein the first metallic material and the second metallic material are copper.

20. The semiconductor structure according to claim 12 , wherein the first metallic material and the second metallic material are cobalt.