IP Library › Granted Patent US 12,660,580
Granted Patent B2
US 12,660,580 · App. 17/679,234 · Granted Jun 16, 2026

Selective barrier layer deposition using blocking layers

Inventors: Chin-Lung Chung (Taoyuan City, TW); Ching-Fu Yeh (Hsinchu City, TW); Shin-Yi Yang (New Taipei City, TW); Ming-Han Lee (Taipei, TW); Ting-Ya Lo (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10W20/034H10W20/035H10W20/0765H10W20/42H10W20/425H10W20/48H10W20/072H10W20/075H10W20/455H10W20/46
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Quick Facts
Patent No.
US 12,660,580
App. No.
17/679,234
Granted
Jun 16, 2026
Kind
B2
Abstract

An interconnection structure includes a conductive feature disposed in a first dielectric material, a first etch stop layer disposed over the first dielectric material, a second dielectric material disposed on the first etch stop layer, a conductive via extending through the second dielectric material and the first etch stop layer and in contact with at least a portion of the conductive feature, a first barrier layer disposed between the second dielectric material and the conductive via, a first liner disposed between and in contact with the first barrier layer and the conductive via, a third dielectric material disposed over the second dielectric material, a conductive line disposed in the third dielectric material and in direct contact with the conductive via, a second barrier layer disposed on the second dielectric material and in contact with the first barrier layer and the conductive line, and a second liner disposed between and in contact with the second barrier layer and the conductive line, wherein the second liner is separated from the first liner.

Claims (56)

1 . A method for forming an interconnection structure, comprising:

forming a first conductive feature in a first dielectric material;

forming a first etch stop layer on the first dielectric material;

forming a second dielectric material on the first etch stop layer;

forming a first opening through the second dielectric material and the first etch stop layer to expose a top surface of the first conductive feature, the first opening having a first dimension;

forming a first blocking layer on the top surface of the first conductive feature;

selectively forming a first barrier layer on surfaces of the second dielectric material and the first etch stop layer in the first opening while the first blocking layer prevents formation of the first barrier layer on the top surface of the first conductive feature;

removing the first blocking layer;

forming a second blocking layer on the top surface of the first conductive feature;

selectively forming a first liner on surfaces of the first barrier layer while the second blocking layer prevents formation of the first liner on the top surface of the first conductive feature;

removing the second blocking layer to expose the top surface of the first conductive feature; and

forming a first conductive material in the first opening so that a portion of the first conductive material is in direct contact with the first conductive feature.

2 . The method of claim 1 , wherein the first barrier layer is formed so that a bottom of the first barrier layer is disposed on a portion of the first blocking layer.

3 . The method of claim 2 , wherein the first blocking layer is removed so that a spacing is formed between the bottom of the first barrier layer and a portion of the top surface of the first conductive feature.

4 . The method of claim 3 , wherein the first conductive material is formed such that a portion of the first conductive material is extended into the spacing.

5 . The method of claim 2 , wherein the first etch stop layer is formed by:

forming a first layer on the first dielectric material;

forming a second layer on the first layer;

forming a third layer on the second layer; and

forming a fourth layer on the third layer.

6 . The method of claim 5 , wherein the bottom of the first barrier layer is at or near an interface defined by the first layer and the second layer.

7 . The method of claim 5 , wherein the first layer and the third layer comprise aluminum oxide, and the second layer and the fourth layer comprise silicon carbide.

8 . The method of claim 7 , wherein the fourth layer is an oxygen-doped silicon carbide.

9 . The method of claim 1 , further comprising:

forming a second opening in the second dielectric material, wherein the first opening is a via opening, and the second opening is a trench opening.

10 . The method of claim 1 , wherein the first and the second blocking layers comprise one or more self-assembled monolayers (SAMs) having a head group and a tail group.

11 . The method of claim 10 , wherein the head group comprises an azole group-containing compound or a compound terminated with an alkyne group.

12 . The method of claim 11 , wherein the head group comprises a highly hydrophobic long alkyl chain.

13 . The method of claim 1 , wherein the first barrier layer is selectively formed on the second dielectric material through self-limiting surface reactions by ALD process and/or MLD process.

14 . A method for forming an interconnection structure, comprising:

forming a first conductive feature in a first dielectric material, wherein the first conductive feature has three surfaces in contact with a first liner layer, and a first barrier layer is disposed between the first liner layer and in contact with the first dielectric material and in contact with the first dielectric material;

forming a first etch stop layer on the first dielectric material;

forming a second dielectric material on the first etch stop layer;

forming a first opening through the second dielectric material and the first etch stop layer to expose a top surface of the first conductive feature and a top surface of the first liner layer;

forming a first blocking layer on the top surfaces of the first conductive feature and the first liner layer;

selectively forming a second barrier layer on surfaces of the second dielectric material and the first etch stop layer in the first opening while the first blocking layer prevents formation of the second barrier layer on the top surfaces of the first conductive feature and the first liner layer;

removing the first blocking layer to expose the top surface of the first conductive feature and the top surface of the first liner layer;

forming a second blocking layer on the top surface of the first conductive feature and the top surface of the first liner layer;

removing the second blocking layer to expose the top surface of the first conductive feature and the top surface of the first liner layer; and

forming a first conductive material in the first opening so that a portion of the first conductive material is in direct contact with the first conductive feature and the first liner layer.

15 . The method of claim 14 , wherein the second barrier layer is formed so that a bottom of the second barrier layer is disposed on a portion of the first blocking layer.

16 . The method of claim 15 , wherein the first blocking layer is removed so that a spacing is formed between the bottom of the second barrier layer and portions of the top surfaces of the first conductive feature and the first liner layer.

17 . The method of claim 16 , wherein the first conductive material is formed such that a portion of the first conductive material is extended into the spacing.

18 . A method for forming an interconnection structure, comprising:

forming a first conductive feature in a first dielectric material, the first conductive feature having a top surface; forming a first etch stop layer on the first dielectric material and the top surface of the first conductive feature;

forming a second dielectric material on the first etch stop layer;

forming a first opening through the second dielectric material and the first etch stop layer to expose the top surface of the first conductive feature;

forming a first blocking layer on the top surface of the first conductive feature;

conformally forming a first barrier layer on sidewalls of the first opening while the first blocking layer prevents formation of the first barrier layer on the top surface of the first conductive feature;

removing the first blocking layer to form a spacing between a bottom of the first barrier layer and the top surface of the first conductive feature;

forming a second blocking layer on the top surface of the first conductive feature;

conformally forming a first liner on surfaces of the first barrier layer while the second blocking layer prevents formation of the first liner on the top surface of the first conductive feature;

removing the second blocking layer to form a spacing between a bottom of the first liner and the top surface of the first conductive feature, wherein the bottom of the first liner is spaced apart from the top surface of the first conductive feature by a distance corresponding to a thickness of the second blocking layer; and

forming a first conductive material in the first opening so that a portion of the first conductive material is in direct contact with the top surface of the first conductive feature and extends into the spacing under the first liner.

19 . The method of claim 18 , wherein the first etch stop layer comprises multiple layers including aluminum oxide and silicon carbide.

20 . The method of claim 18 , wherein the first blocking layer and the second blocking layer each comprise a self-assembled monolayer having an azole group-containing compound.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2022
From: CHUNG, CHIN-LUNG; YEH, CHING-FU; YANG, SHIN-YI; LEE, MING-HAN; LO, TING-YA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 059086/0682 →
Continuity (2)
Provisional Application 63279052 · Nov 12, 2021
Related Publication 20230154791A1 · May 18, 2023
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