Methods and circuits for asymmetric distribution of channel equalization between devices
A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
1. An integrated circuit comprising:
a transmit equalizer having a transmit-equalizer control port, the transmit equalizer to equalize a first signal resulting in a first equalized signal, using a first range of coefficients, applied to the transmit-equalizer control port;
a receive port to receive a corrupted second signal that includes inter-symbol interference;
a signal monitor to provide a measure of the inter-symbol interference of the second signal; and
equalization control circuitry coupled between the signal monitor and the transmit-equalizer control port.
2. The integrated circuit of claim 1 , further comprising a receive equalizer having a receive-equalizer control port, the receive equalizer to equalize the inter-symbol interference of the second signal.
3. The integrated circuit of claim 2 , wherein the equalization control circuitry is coupled to the receive-equalizer control port.
4. The integrated circuit of claim 2 , wherein the signal monitor is coupled to the receive port via the receive equalizer.
5. The integrated circuit of claim 1 , wherein the transmit equalizer includes a pre-cursor filter tap, and wherein the equalization control circuitry controls the pre-cursor filter tap based upon the measure of inter-symbol interference of the second signal.
6. A method of transmitting a first signal from an integrated circuit, the method comprising:
receiving a corrupted second signal at a receiver pad of the integrated circuit;
measuring corruption of the second signal, the corruption including inter-symbol interference;
deriving a transmit coefficient from the measured corruption; and
adjusting the first signal using the transmit coefficient.
7. The method of claim 6 , further comprising deriving a receive coefficient from the measured corruption.
8. The method of claim 7 , further comprising calculating the transmit coefficient from the receive coefficient.
9. The method of claim 6 , further comprising measuring an amplitude of the corrupted second signal, wherein the deriving of the transmit coefficient is based at least in part on the amplitude.
10. The method of claim 6 , wherein first signal and the corrupted second signal are conveyed over a bidirectional channel.
11. The method of claim 6 , further comprising periodically updating the transmit coefficient.
12. The method of claim 6 , wherein the integrated circuit is a first integrated circuit and the second signal is received from a second integrated circuit, the method further comprising:
receiving a corrupted third signal at a receiver pad of the first integrated circuit from a third integrated circuit;
measuring second corruption of the third signal, the second corruption including second inter-symbol interference; and
deriving a second transmit coefficient from the measured second corruption; and
transmitting to the third integrated circuit using the second transmit coefficient.
13. An integrated circuit comprising:
a transmitter having a transmit coefficient port, for receiving a transmit coefficient, and an output port for transmitting a first signal over a communication lane;
a receiver for receiving a corrupted second signal over the communication lane; and
means for deriving the transmit coefficient from the corrupted second signal.
14. The integrated circuit of claim 13 , wherein the corrupted second signal includes inter-symbol interference, and wherein the receiver further comprises a receive equalizer, the integrated circuit further comprising means for adjusting the receive equalizer responsive to the inter-symbol interference.
15. A non-transitory computer-readable medium having stored thereon a representation of a receiver, the representation comprising:
first data representing a transmit equalizer having a transmit-equalizer control port, the transmit equalizer to equalize a first signal resulting in a first equalized signal, using a first range of coefficients, applied to the transmit-equalizer control port;
second data representing a receive port to receive a corrupted second signal that includes inter-symbol interference;
third data representing a signal monitor to provide a measure of the inter-symbol interference of the second signal; and
fourth data representing equalization control circuitry coupled between the signal monitor and the transmit-equalizer control port.
16. The computer-readable medium of claim 15 , the representation further comprising fifth data representing a receive equalizer having a receive-equalizer control port, the receive equalizer to equalize the inter-symbol interference of the second signal.
17. The computer-readable medium of claim 16 , wherein the equalization control circuitry is represented as coupled to the receive-equalizer control port.
18. The computer-readable medium of claim 16 , wherein the signal monitor is represented as coupled to the receive port via the receive equalizer.
19. The computer-readable medium of claim 15 , wherein the first data represents the transmit equalizer as including a pre-cursor filter tap, and wherein the equalization control circuitry is represented as controlling the pre-cursor filter tap based upon the measure of inter-symbol interference of the second signal.