Package structure with lid and method for forming the same

1. A package structure, comprising:

a semiconductor die formed over a first side of an interconnect structure, wherein the semiconductor die has a first height;

a first stacked die package structure formed over the first side of the interconnect structure, wherein the first stacked die package structure has a second height, and the second height is greater than the first height;

a lid structure formed over the semiconductor die and the first stacked die package structure, wherein the lid comprises a main portion and a protruding portion extending from the main portion, and the protruding portion is directly over the semiconductor die;

an underfill layer below the first stacked die package structure, and covering the sidewalls of the semiconductor die; and

a package layer formed between the semiconductor die and the first stacked die package structure, wherein sidewalls of the first stacked die package structure are separated from the package layer by the underfill layer, and the package layer is in contact with sidewalls of the semiconductor die.

2. The package structure as claimed in claim 1 , wherein the protruding portion has a bottom surface, the bottom surface of the protruding portion is higher than a top surface of the semiconductor die and lower than a top surface of the first stacked die package structure.

3. The package structure as claimed in claim 1 , wherein the first stacked die package structure comprises a plurality of memory dies.

4. The package structure as claimed in claim 3 , wherein the semiconductor die has a different function from each of the plurality of the memory dies.

5. The package structure as claimed in claim 1 , further comprising:

an adhesive layer formed below the lid structure, wherein a bottom portion of the adhesive layer is lower than a top surface of the first stacked die package structure.

6. The package structure as claimed in claim 5 , wherein a sidewall surface of the bottom portion of the adhesive layer is aligned with a sidewall surface of the semiconductor die.

7. The package structure as claimed in claim 1 , further comprising:

a plurality of first conductive connectors formed on the first side of the interconnect structure, wherein there is a first gap between two adjacent first conductive connectors;

a plurality of second conductive connectors formed below a second side of the interconnect structure, wherein there is a second gap between two adjacent second conductive connectors, and the second gap is greater than the first gap.

8. The package structure as claimed in claim 1 , further comprising:

a second stacked die package structure formed over the first side of the interconnect structure, wherein the first stacked die package structure has a third height, and the third height is higher than the first height.

9. The package structure as claimed in claim 1 , wherein an interface is between the underfill layer and the package layer, and the interface is lower than a top surface of the semiconductor die.

10. A package structure, comprising:

a semiconductor die formed over a first side of an interconnect structure;

a first stacked die package structure formed over the first side of the interconnect structure, wherein the first stacked die package structure comprises a plurality of memory dies;

a second stacked die package structure formed over the first side of the interconnect structure, wherein the semiconductor die is between the first stacked die package structure and the second stacked die package structure, and the second stacked die package structure comprises a plurality of memory dies;

a lid structure formed over the semiconductor die and the first stacked die package structure, wherein the lid structure has a T-shaped structure, and a bottommost surface of the lid structure is lower than a top surface of the first stacked die package structure; and

an underfill layer between the semiconductor die and the first stacked die package structure, wherein the underfill layer covers sidewalls of the first stacked die, and is positioned between the semiconductor die and the interconnect structure; and

a package layer formed over the underfill layer, wherein an interface is between the underfill layer and the package layer, and the interface is lower than a top surface of the semiconductor die.

11. The package structure as claimed in claim 10 , wherein the semiconductor die has a different function from each of the plurality of the memory dies.

12. The package structure as claimed in claim 10 , further comprising:

an adhesive layer formed below the lid structure, wherein a bottommost surface of the adhesive layer is lower than the top surface of the first stacked die package structure.

13. The package structure as claimed in claim 10 , further comprising:

a plurality of bonding structures between two adjacent memory dies; and

a plurality of through substrate vias (TSVs) formed in each of the memory dies.

14. The package structure as claimed in claim 10 , further comprising:

a plurality of first conductive connectors formed on the first side of the interconnect structure, wherein there is a first gap between two adjacent first conductive connectors;

a plurality of second conductive connectors formed below a second side of the interconnect structure, wherein there is a second gap between two adjacent second conductive connectors, and the second gap is greater than the first gap.

15. A package structure, comprising:

a semiconductor die formed over a first side of an interconnect structure;

a first stacked die package structure formed over the first side of the interconnect structure, wherein the first stacked die package structure comprises a plurality of memory dies;

a lid structure formed over the semiconductor die and the first stacked die package structure, wherein a bottommost surface of the lid structure is higher than a top surface of the semiconductor die and lower than a top surface of the first stacked die package structure;

a package layer disposed between the lid structure and the first stacked die package in a normal direction of the interconnect structure and in contact with sidewalls of the semiconductor die, and separated from sidewalls of the first stacked die package structure; and

an underfill layer below the semiconductor die and in contact with the sidewalls of the first stacked die package structure.

16. The package structure as claimed in claim 15 , further comprising:

a second stacked die package structure formed over the first side of the interconnect structure, wherein the semiconductor die is between the first stacked die package structure and the second stacked die package structure, and the second stacked die package structure comprises a plurality of memory dies.

17. The package structure as claimed in claim 15 , wherein the package layer is formed over the underfill layer, a tilted interface is between the underfill layer and the package layer, and the tilted interface is lower than a top surface of the semiconductor die.

18. The package structure as claimed in claim 15 , wherein the semiconductor die has a first height, the first stacked die package structure has a second height, and the second height is greater than the first height.

19. The package structure as claimed in claim 15 , wherein the underfill layer extends continuously to in contact with a bottom surface of the semiconductor die and a bottom surface of the first stacked die package structure.

20. The package structure as claimed in claim 15 , wherein an interface is between the underfill layer and the package layer, and the interface is lower than a top surface of the semiconductor die.