Split gate non-volatile memory cells with FinFET structure and HKMG memory and logic gates, and method of making same
A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.
1. A memory device, comprising:
a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface;
a memory cell formed on a first fin of the plurality of fins, comprising:
spaced apart first source and first drain regions in the first fin, with a first channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the first source and first drain regions,
a floating gate of polysilicon material that extends along a first portion of the first channel region, wherein the floating gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin,
a select gate of metal material that extends along a second portion of the first channel region, wherein the select gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin,
a control gate of polysilicon material that extends along and is insulated from the floating gate, and
an erase gate of polysilicon material that extends along and is insulated from the first source region;
a logic device formed on a second fin of the plurality of fins, comprising:
spaced apart second source and second drain regions in the second fin, with a second channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the second source and second drain regions, and
a first logic gate of metal material that extends along the second channel region, wherein the first logic gate wraps around the second fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the second fin.
2. The memory device of claim 1 , wherein high K dielectric material is disposed between the select gate and the second portion of the first channel region, and wherein high K dielectric material is disposed between the first logic gate and the second channel region.
3. The memory device of claim 1 , wherein the top surface of the first fin is recessed relative to the top surface of the second fin.
4. The memory device of claim 1 , wherein the top surface of the first fin includes a first raised portion of the substrate relative to a portion of the top surface of the first fin along which the first channel region extends, and wherein the first drain region is formed at least partially in the first raised portion.
5. The memory device of claim 4 , wherein the top surface of the second fin includes second and third raised portions of the substrate relative to a portion of the top surface of the second fin along which the second channel region extends, and wherein the second source region is formed at least partially in the second raised portion and the second drain region is formed at least partially in the third raised portion.
6. The memory device of claim 1 , further comprising:
a third fin of the plurality of fins having a length that extends in a first direction, wherein the first fin has a length that extends in a second direction that is perpendicular to the first direction, and wherein the first source region is formed in the first fin at an intersection of the first and third fins.
7. The memory device of claim 6 , wherein the erase gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, and extends along and is insulated from the first and second side surfaces and the top surface of the third fin.
8. The memory device of claim 1 , wherein the erase gate extends along and is insulated from an upper edge of the floating gate, and wherein the erase gate includes a notch facing the upper edge of the floating gate.
9. The memory device of claim 1 , further comprising:
a second logic device formed on a third fin of the plurality of fins, comprising:
spaced apart third source and third drain regions in the third fin, with a third channel region of the third fin extending along the top surface and the opposing side surfaces of the third fin between the third source and third drain regions, and
a second logic gate that extends along the third channel region, wherein the second logic gate wraps around the third fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the third fin.
10. The memory device of claim 9 , wherein:
the first logic gate is insulated from the second fin by first insulation material;
the second logic gate is insulated from the third fin by second insulation material;
the second insulation material has a thickness that is greater than that of the first insulation material.
11. A method of forming a memory device, comprising:
forming a plurality of upwardly extending fins in an upper surface of a semiconductor substrate, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface;
forming a memory cell on a first fin of the plurality of fins, by:
forming spaced apart first source and first drain regions in the first fin, with a first channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the first source and first drain regions,
forming a floating gate of polysilicon material that extends along a first portion of the first channel region, wherein the floating gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin,
forming a select gate of metal material that extends along a second portion of the first channel region, wherein the select gate wraps around the first fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the first fin,
forming a control gate of polysilicon material that extends along and is insulated from the floating gate, and
forming an erase gate of polysilicon that extends along and is insulated from the first source region;
forming a logic device on a second fin of the plurality of fins, by:
forming spaced apart second source and second drain regions in the second fin, with a second channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the second source and second drain regions, and
forming a first logic gate of metal material that extends along the second channel region, wherein the first logic gate wraps around the second fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the second fin.
12. The method of claim 11 , wherein the forming of the select gate, the erase gate and the first logic gate comprises:
forming a polysilicon layer over the substrate;
removing portions of the polysilicon layer such that a first block of the polysilicon layer extends along and is insulated from the first source region, a second block of the polysilicon layer extends along and is insulated from the second portion of the first channel region, and a third block of the polysilicon layer extends along and is insulated from the second channel region;
removing and replacing the second block of the polysilicon layer with a first block of metal material; and
removing and replacing the third block of the polysilicon layer with a second block of metal material;
wherein the first block of the polysilicon layer is the erase gate, the first block of metal material is the select gate and the second block of metal material is the first logic gate.
13. The method of claim 12 , further comprising:
forming an insulation layer over the erase gate and the control gate before the removing of the second and third blocks of the polysilicon layer.
14. The method of claim 11 , wherein the forming of the select gate includes forming high K dielectric material disposed between the select gate and the second portion of the first channel region, and wherein the forming of the first logic gate includes forming high K dielectric material disposed between the first logic gate and the second channel region.
15. The method of claim 11 , wherein the top surface of the first fin is recessed relative to the top surface of the second fin.
16. The method of claim 11 , further comprising:
forming a first raised portion in the top surface of the first fin relative to a portion of the top surface of the first fin along which the first channel region extends, wherein the first drain region is formed at least partially in the first raised portion.
17. The method of claim 16 , further comprising:
forming a second raised portion in the top surface of the second fin relative to a portion of the top surface of the second fin along which the second channel region extends, wherein the second source region is formed at least partially in the second raised portion;
forming a third raised portion in the top surface of the second fin relative to the portion of the top surface of the second fin along which the second channel region extends, wherein the second drain region is formed at least partially in the third raised portion.
18. The method of claim 11 , further comprising:
forming a third fin of the plurality of fins having a length that extends in a first direction, wherein the first fin has a length that extends in a second direction that is perpendicular to the first direction, and wherein the first source region is formed in the first fin at an intersection of the first and third fins.
19. The method of claim 18 , wherein the erase gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, and extends along and is insulated from the first and second side surfaces and the top surface of the third fin.
20. The method of claim 11 , wherein the erase gate extends along and is insulated from an upper edge of the floating gate, and wherein the erase gate includes a notch facing the upper edge of the floating gate.
21. The method of claim 11 , further comprising:
forming a second logic device on a third fin of the plurality of fins, by:
forming spaced apart third source and third drain regions in the third fin, with a third channel region of the third fin extending along the top surface and the opposing side surfaces of the third fin between the third source and third drain regions, and
forming a second logic gate that extends along the third channel region, wherein the second logic gate wraps around the third fin so as to be adjacent to and insulated from the first and second side surfaces and the top surface of the third fin.
22. The method of claim 21 , wherein:
the first logic gate is insulated from the second fin by first insulation material;
the second logic gate is insulated from the third fin by second insulation material;
the second insulation material has a thickness that is greater than that of the first insulation material.