Memory cell with floating gate, coupling gate and erase gate, and method of making same
A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between. A floating gate is disposed over and insulated from the channel region, wherein the conductivity of the channel region is solely controlled by the floating gate. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate. Logic devices are formed on the same substrate. Each logic device has source and drain regions with a channel region extending there between, and a logic gate disposed over and controlling the logic device's channel region.
1. A memory device, comprising:
a semiconductor substrate;
a first source region and a first drain region formed in the substrate, with a first channel region of the substrate extending there between;
a floating gate disposed over and insulated from the first channel region, wherein a conductivity of the first channel region is solely controlled by the floating gate;
a control gate disposed over and insulated from the floating gate;
an erase gate disposed over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate;
a second source region and a second drain region formed in the substrate, with a second channel region of the substrate extending there between;
a first logic gate disposed over and insulated from the second channel region, wherein the first logic gate controls a conductivity of the second channel region;
a third source region and a third drain region formed in the substrate, with a third channel region of the substrate extending there between; and
a second logic gate disposed over and insulated from the third channel region, wherein the second logic gate controls a conductivity of the third channel region;
wherein:
the first logic gate is insulated from the second channel region by first insulation having a first thickness,
the second logic gate is insulated from the third channel region by second insulation having a second thickness greater than the first thickness,
the third source region extends deeper into the substrate relative to a surface of the substrate than does the second source region, and
the third drain region extends deeper into the substrate relative to the surface of the substrate than does the second drain region.
2. A memory device, comprising:
a semiconductor substrate;
a first source region formed in the substrate;
first and second drain regions formed in the substrate, wherein a first channel region of the substrate extends between the first drain region and the first source region, and wherein a second channel region of the substrate extends between the second drain region and the first source region;
a first floating gate disposed over and insulated from the first channel region, wherein a conductivity of the first channel region is solely controlled by the first floating gate;
a second floating gate disposed over and insulated from the second channel region, wherein a conductivity of the second channel region is solely controlled by the second floating gate;
a first control gate disposed over and insulated from the first floating gate;
a second control gate disposed over and insulated from the second floating gate;
an erase gate disposed over and insulated from the first source region, wherein the erase gate includes a first notch that faces and is insulated from an edge of the first floating gate and a second notch that faces and is insulated from an edge of the second floating gate;
a second source region and a third drain region formed in the substrate, with a third channel region of the substrate extending there between;
a first logic gate disposed over and insulated from the third channel region, wherein the first logic gate controls a conductivity of the third channel region;
a third source region and a fourth drain region formed in the substrate, with a fourth channel region of the substrate extending there between;
a second logic gate disposed over and insulated from the fourth channel region, wherein the second logic gate controls a conductivity of the fourth channel region;
wherein:
the first logic gate is insulated from the third channel region by first insulation having a first thickness,
the second logic gate is insulated from the fourth channel region by second insulation having a second thickness greater than the first thickness,
the third source region extends deeper into the substrate relative to a surface of the substrate than does the second source region, and
the fourth drain region extends deeper into the substrate relative to the surface of the substrate than does the third drain region.
3. A method, comprising:
forming a first source region and a first drain region in a semiconductor substrate, with a first channel region of the substrate extending there between;
forming a floating gate over and insulated from the first channel region, wherein a conductivity of the first channel region is solely controlled by the floating gate;
forming a control gate over and insulated from the floating gate;
forming an erase gate over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate;
forming a second source region and a second drain region in the substrate, with a second channel region of the substrate extending there between;
forming a first logic gate over and insulated from the second channel region, wherein the first logic gate controls a conductivity of the second channel region;
forming a third source region and a third drain region in the substrate, with a third channel region of the substrate extending there between;
forming a second logic gate over and insulated from the third channel region, wherein the second logic gate controls a conductivity of the third channel region;
wherein:
the first logic gate is insulated from the second channel region by first insulation having a first thickness,
the second logic gate is insulated from the third channel region by second insulation having a second thickness greater than the first thickness,
the third source region extends deeper into the substrate relative to a surface of the substrate than does the second source region, and
the third drain region extends deeper into the substrate relative to the surface of the substrate than does the second drain region.
4. The method of claim 3 , wherein the forming of the erase gate, the first logic gate and the second logic gate comprises:
forming a polysilicon layer over the substrate;
etching the polysilicon layer to form separate first, second and third blocks of the polysilicon layer, wherein the first block is the erase gate, the second block is the first logic gate and the third block is the second logic gate.
5. A method, comprising:
forming a first source region in a semiconductor substrate;
forming first and second drain regions in the substrate, wherein a first channel region of the substrate extends between the first drain region and the first source region, and wherein a second channel region of the substrate extends between the second drain region and the first source region;
forming a first floating gate over and insulated from the first channel region, wherein a conductivity of the first channel region is solely controlled by the first floating gate;
forming a second floating gate over and insulated from the second channel region, wherein a conductivity of the second channel region is solely controlled by the second floating gate;
forming a first control gate over and insulated from the first floating gate;
forming a second control gate over and insulated from the second floating gate;
forming an erase gate over and insulated from the first source region, wherein the erase gate includes a first notch that faces and is insulated from an edge of the first floating gate and a second notch that faces and is insulated from an edge of the second floating gate;
forming a second source region and a third drain region in the substrate, with a third channel region of the substrate extending there between;
forming a first logic gate over and insulated from the third channel region, wherein the first logic gate controls a conductivity of the third channel region;
forming a third source region and a fourth drain region in the substrate, with a fourth channel region of the substrate extending there between;
forming a second logic gate over and insulated from the fourth channel region, wherein the second logic gate controls a conductivity of the fourth channel region;
wherein:
the first logic gate is insulated from the third channel region by first insulation having a first thickness,
the second logic gate is insulated from the fourth channel region by second insulation having a second thickness greater than the first thickness,
the third source region extends deeper into the substrate relative to a surface of the substrate than does the second source region, and
the fourth drain region extends deeper into the substrate relative to the surface of the substrate than does the third drain region.
6. The method of claim 5 , wherein the forming of the erase gate, the first logic gate and the second logic gate comprises:
forming a polysilicon layer over the substrate;
etching the polysilicon layer to form separate first, second and third blocks of the polysilicon layer, wherein the first block is the erase gate, the second block is the first logic gate and the third block is the second logic gate.