System and method for storing and retrieving multibit data in non-volatile memory using current multipliers
View Patent ↗A memory device includes memory cells each configured to produce an output current during a read operation. Circuitry is configured to, for each of the memory cells, generate a read value based on the output current of the memory cell. Circuitry is configured to, for each of the memory cells, multiply the read value for the memory cell by a multiplier to generate a multiplied read value, wherein the multiplier for each of the memory cells is different from the multipliers for any others of the memory cells. Circuitry is configured to sum the multiplied read values. The read values can be electrical currents, electrical voltages or numerical values. Alternatively, added constant values can be used instead of multipliers. The multipliers or constants can be applied to read currents from individual cells, or read currents on entire bit lines.
1. A memory device, comprising:
memory cells each configured to produce an output current during a read operation;
circuitry configured to, for each of the memory cells, generate a read value based on the output current of the memory cell;
circuitry configured to, for each of the memory cells, multiply the read value for the memory cell by a multiplier to generate a multiplied read value, wherein the multiplier for each of the memory cells is different from the multipliers for any others of the memory cells, and wherein the multipliers follow a progression; and
circuitry configured to sum the multiplied read values.
2. The memory device of claim 1 , wherein the circuitry configured to generate the read values is configured to generate the read values by amplifying the output currents of the memory cells, and wherein the read values are electrical currents.
3. The memory device of claim 1 , wherein the circuitry configured to generate the read values is configured to generate the read values by generating voltages based on the output currents of the memory cells, and wherein the read values are voltages.
4. The memory device of claim 1 , wherein the circuitry configured to generate the read values is configured to generate the read values by generating numerical values based on the output currents of the memory cells.
5. The memory device of claim 1 , wherein the multipliers follow the progression according to 2X, where X are non-negative integers.
6. The memory device of claim 1 , wherein the multipliers follow the progression according to X·K, where X are positive integers and K is a constant value.
7. A memory device, comprising:
memory cells each configured to produce an output current during a read operation;
circuitry configured to, for each of the memory cells, generate a read value based on the output current of the memory cell;
circuitry configured to, for each of the memory cells, add a constant value to the read value to generate an added read value, wherein the constant value for each of the memory cells is different from the constant values for any others of the memory cells; and
circuitry configured to sum the added read values.
8. The memory device of claim 7 , wherein the circuitry configured to generate the read values is configured to generate the read values by amplifying the output currents of the memory cells, and wherein the read values are electrical currents.
9. The memory device of claim 7 , wherein the circuitry configured to generate the read values is configured to generate the read values by generating voltages based on the output currents of the memory cells, and wherein the read values are voltages.
10. The memory device of claim 7 , wherein the circuitry configured to generate the read values is configured to generate the read values by generating numerical values based on the output currents of the memory cells.
11. A memory device, comprising:
a plurality of memory cells arranged in rows and columns, wherein each of the memory cells is configured to produce an output current during a read operation;
a plurality of bit lines, wherein each of the bit lines is connected to a respective one of the columns of the memory cells for receiving the output currents from the respective one column of the memory cells;
circuitry configured to, for each of the bit lines, generate a read value based on the received output currents by the bit line;
circuitry configured to, for each of the bit lines, multiply the read value for the bit line by a multiplier to generate a multiplied read value, wherein the multiplier for each of the bit lines is different from the multipliers for any others of the bit lines, and wherein the multipliers follow a progression; and
circuitry configured to sum the multiplied read values.
12. The memory device of claim 11 , wherein the circuitry configured to generate the read values is configured to generate the read values by amplifying the output currents of the bit lines, and wherein the read values are electrical currents.
13. The memory device of claim 11 , wherein the circuitry configured to generate the read values is configured to generate the read values by generating voltages based on the output currents of the bit lines, and wherein the read values are voltages.
14. The memory device of claim 11 , wherein the circuitry configured to generate the read values is configured to generate the read values by generating numerical values based on the output currents of the bit lines.
15. The memory device of claim 11 , wherein the multipliers follow the progression according to 2X, where X are non-negative integers.
16. The memory device of claim 11 , wherein the multipliers follow the progression according to X·K, where X are positive integers and K is a constant value.
17. A memory device, comprising:
a plurality of memory cells arranged in rows and columns, wherein each of the memory cells is configured to produce an output current during a read operation;
a plurality of bit lines, wherein each of the bit lines is connected to a respective one of the columns of the memory cells for receiving the output currents from the respective one column of the memory cells;
circuitry configured to, for each of the bit lines, generate a read value based on the received output currents by the bit line;
circuitry configured to, for each of the bit lines, add a constant value to the read value for the bit line to generate an added read value, wherein the constant value for each of the bit lines is different from the constant values for any others of the bit lines; and
circuitry configured to sum the added read values.
18. The memory device of claim 17 , wherein the circuitry configured to generate the read values is configured to generate the read values by amplifying the output currents of the bit lines, and wherein the read values are electrical currents.
19. The memory device of claim 17 , wherein the circuitry configured to generate the read values is configured to generate the read values by generating voltages based on the output currents of the bit lines, and wherein the read values are voltages.
20. The memory device of claim 17 , wherein the circuitry configured to generate the read values is configured to generate the read values by generating numerical values based on the output currents of the bit lines.