Silicon carbide semiconductor device
A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.
1. A silicon carbide semiconductor device comprising:
a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface; and
a gate insulating film provided on the first main surface,
the silicon carbide substrate including
a first body region being in contact with the gate insulating film at the first main surface and having a first conductivity type,
a second body region being in contact with the gate insulating film at the first main surface and having the first conductivity type,
a drift region having a second conductivity type different from the first conductivity type, and
a JFET region provided between the first body region and the second body region in a direction parallel to the first main surface, provided between the gate insulating film and the drift region in a direction perpendicular to the first main surface, and having the second conductivity type,
the JFET region and the drift region each having an impurity capable of providing the second conductivity type,
a density of threading dislocations in the first main surface being not less than 100 cm −2 and not more than 10000 cm −2 ,
a concentration of the impurity included in the JFET region being lower than a concentration of the impurity included in the drift region,
the first conductivity type being p type and the second conductivity type being n type.
2. The silicon carbide semiconductor device according to claim 1 , wherein
the concentration of the impurity included in the JFET region is not less than 1×10 14 cm −3 and not more than 1×10 16 cm −3 .
3. The silicon carbide semiconductor device according to claim 1 , wherein
in the JFET region, the concentration of the impurity decreases from the second main surface toward the first main surface.
4. The silicon carbide semiconductor device according to claim 1 , wherein
in the drift region, the concentration of the impurity decreases from the second main surface toward the first main surface.