Method of clock gate analysis for improved efficiency of electronic circuitry system designs and related systems, methods and devices
Systems and methods described in this disclosure relate, generally, to analyzing electronic circuitry, and more specifically, to analyzing efficiency of clock gating in electronic circuitry. Analysis may include identifying wasted propagation of clock signals by clock gates and/or for a circuitry as a whole. In some embodiments, modified gating logic may be determined that improves clock gating efficiency, for example, by eliminating at least some wasted propagation of clock signals.
1. A method of analyzing an electronic system, comprising:
identifying propagating clock cycles of a clock gate;
identifying idle clock cycles of a gated-device operatively coupled to the clock gate;
identifying wasted propagation clock cycles responsive to an overlap of the propagating clock cycles and the idle clock cycles;
configuring a modified clock gating logic responsive to the wasted propagation clock cycles;
comparing a first activity of the gated-device to a second activity of the gated-device; and
confirming the first activity and the second activity are consistent.
2. The method of claim 1 , wherein comparing the first activity of the gated-device to the second activity of the gated-device comprises:
determining the first activity of the gated-device responsive to activity associated with the gated-device prior to configuring the modified clock gating logic; and
determining the second activity of the gated-device responsive to activity associated with the gated-device subsequent to configuring the modified clock gating logic.
3. The method of claim 1 , wherein identifying idle clock cycles of a gated-device comprises:
identifying activity on a data path that corresponds to a clock path that includes the clock gate and the gated-device; and
identifying the idle clock cycles responsive to the identified activity.
4. The method of claim 1 , wherein identifying the propagating clock cycles of the clock gate comprises identifying a series of clock cycles during which the clock gate is propagating a received clock.
5. The method of claim 1 , wherein the identifying the wasted propagation clock cycles responsive to the overlap of the propagating clock cycles and the idle clock cycles comprises:
identifying a first series of clock cycles corresponding to the propagating clock cycles of the clock gate;
identifying a second series of clock cycles corresponding to the idle clock cycles of the gated-device; and
identifying at least one clock cycle that is the same for the first series of clock cycles and the second series of clock cycles.
6. The method of claim 1 , wherein configuring the modified clock gating logic responsive to the wasted propagation clock cycles comprises configuring the modified clock gating logic to not propagate a received clock for at least one of the wasted propagation clock cycles.
7. The method of claim 3 , wherein identifying the idle clock cycles comprises observing one or more state changes at an output of the gated-device.
8. The method of claim 3 , wherein identifying the idle clock cycles further comprises:
identifying clock cycles corresponding to the observed state changes; and
identifying a series of clock cycles between two consecutive state changes of observed state changes.
9. A system for analyzing electronic circuitry, comprising:
a non-transitory storage medium configured to store electronic files of waveforms corresponding to operation of clock gates and gated-devices of an electronic circuitry;
a processor for processing the electronic files of waveforms stored at the non-transitory storage medium, wherein the processor is configured to:
identify propagating clock cycles of a clock gate;
identify idle clock cycles of a gated-device operatively coupled to the clock gate;
identify wasted propagation clock cycles responsive to an overlap of the propagating clock cycles and the idle clock cycles;
configure a modified clock gating logic responsive to the wasted propagation clock cycles;
compare a first activity of the gated-device to a second activity of the gated-device; and
confirm the first activity and the second activity are consistent.
10. The system of claim 9 , wherein the processor is configured to compare the first activity of the gated-device to the second activity of the gated-device by:
determining the first activity of the gated-device responsive to activity associated with the gated-device prior to configuring the modified clock gating logic; and
determining the second activity of the gated-device responsive to activity associated with the gated-device subsequent to configuring the modified clock gating logic.
11. The system of claim 9 , wherein the processor is configured to identify the propagation clock cycles of the clock gate by identifying a series of clock cycles during which the clock gate is open.
12. The system of claim 9 , wherein the processor is configured to identify the wasted propagation clock cycles responsive to the overlap of the propagating clock cycles and the idle clock cycles by:
identifying a first series of clock cycles corresponding to the propagating clock cycles of the clock gate;
identifying a second series of clock cycles corresponding to the idle clock cycles of the gated-device; and
identifying at least one clock cycle that is the same for the first series of clock cycles and the second series of clock cycles.
13. The system of claim 9 , wherein the processor is configured to configure the modified clock gating logic responsive to the wasted propagation clock cycles by configuring the modified clock gating logic to close the clock gate for at least one of the wasted propagation clock cycles.
14. The system of claim 10 , wherein the processor is configured to identify the idle clock cycles of a gated-device by:
identifying activity on a data path that corresponds to a clock path that includes the clock gate and the gated-device; and
identifying the idle clock cycles responsive to the identified activity.
15. The system of claim 14 , wherein the processor is configured to identify the idle clock cycles comprises observing one or more state changes at an output of the gated-device.
16. The system of claim 14 , wherein the processor is configured to identify the idle clock cycles further by:
identifying clock cycles corresponding to observed state changes; and
identifying a series of clock cycles between two consecutive state changes of observed state changes.
17. A computer program product, comprising:
a computer-readable medium; and
instructions stored on the computer-readable medium, the instructions configured to enable a processor to perform operations of:
identifying propagating clock cycles of a clock gate;
identifying idle clock cycles of a gated-device operatively coupled to the clock gate;
identifying wasted propagation clock cycles responsive to an overlap of the propagating clock cycles and the idle clock cycles;
configuring a modified clock gating logic responsive to the wasted propagation clock cycles;
comparing a first activity of the gated-device to a second activity of the gated-device; and
confirming the first activity and the second activity are consistent.
18. The computer program product of claim 17 , wherein the instructions are configured to enable the processor to compare the first activity of the gated-device to the second activity of the gated-device by:
determining the first activity of the gated-device responsive to activity associated with the gated-device prior to configuring the modified clock gating logic; and
determining the second activity of the gated-device responsive to activity associated with the gated-device subsequent to configuring the modified clock gating logic.
19. The computer program product of claim 17 , wherein the instructions are configured to enable the processor to identify the propagation clock cycles of the clock gate by identifying a series of clock cycles during which the clock gate is open.
20. The computer program product of claim 17 , wherein the instructions are configured to enable the processor to identify the wasted propagation clock cycles responsive to the overlap of the propagating clock cycles and the idle clock cycles by:
identifying a first series of clock cycles corresponding to the propagating clock cycles of the clock gate;
identifying a second series of clock cycles corresponding to the idle clock cycles of the gated-device; and
identifying at least one clock cycle that is the same for the first series of clock cycles and the second series of clock cycles.
21. The computer program product of claim 17 , wherein the instructions are configured to enable the processor to configure the modified clock gating logic responsive to the wasted propagation clock cycles by configuring the modified clock gating logic to close the clock gate for at least one of the wasted propagation clock cycles.
22. The computer program product of claim 18 , wherein the instructions are configured to enable the processor to identify the idle clock cycles of a gated-device by:
identifying activity on a data path that corresponds to a clock path that includes the clock gate and the gated-device; and
identifying the idle clock cycles responsive to the identified activity.
23. The computer program product of claim 22 , wherein the instructions are configured to enable the processor to identify the idle clock cycles comprises observing one or more state changes at an output of the gated-device.
24. The computer program product of claim 22 , wherein the instructions are configured to enable the processor to identify the idle clock cycles further by:
identifying clock cycles corresponding to observed state changes; and
identifying a series of clock cycles between two consecutive state changes of the observed state changes.
25. A method of analyzing an electronic circuitry design, comprising:
identifying logic cells comprising a gate-level logic model of an electronic circuitry design;
generating first simulation commands for simulating the electronic circuitry design responsive to the identified logic cells;
performing a first simulation responsive to generating the first simulation commands;
identifying clock gate behavior responsive to performing the first simulation;
generating second simulation commands for simulating the electronic circuitry design responsive to identifying the clock gate behavior;
performing a second simulation responsive to generating the second simulation commands;
collecting dynamic efficiency information for the electronic circuitry design responsive to performing the second simulation; and
scoring one or more of the electronic circuitry design, clock-gates of the electronic circuitry design, and gated-devices of the electronic circuitry design responsive to collecting the dynamic efficiency information.
26. The method of claim 25 , wherein collecting dynamic efficiency information comprises collecting one or more of:
a number of clock cycles where a gated-device is active;
a number of cycles where a gated-device is static and a clock-gate corresponding to such gated-device is propagating a received clock; and
a number of gated-devices in a fan out of a clock gate.
27. The method of claim 25 , wherein the generating the first simulation commands for simulating the electronic circuitry design responsive to the identified logic cells comprises:
identifying clock gates described in the logic cells; and
generating the first simulation commands responsive to the identified clock gates.
28. The method of claim 25 , wherein the generating the first simulation commands responsive to identified clock gates comprises generating simulation commands for simulating signaling changes at the identified clock gates.
29. The method of claim 25 , wherein identifying clock gate behavior responsive to performing the first simulation comprises identifying sampling frequencies for performing a simulation of clock gates and gated-devices of the electronic circuitry design.
30. The method of claim 25 , wherein generating second simulation commands for simulating the electronic circuitry design responsive to identifying the clock gate behavior comprises:
generating simulation commands for simulating clock gates and gated-devices of the electronic circuitry design using a sampling frequency.
31. The method of claim 28 , wherein generating simulation commands for simulating signaling changes at the identified clock gates comprises: generating the simulation commands for simulating signaling changes at the identified clock gates but not for simulating signaling changes at other devices the electronic circuitry design.
32. The method of claim 29 , wherein identifying sampling frequencies for performing the simulation of the clock gates and the gated-devices of the electronic circuitry design comprises:
identifying a lowest clock frequency and a highest clock frequency during an analysis period; and
determining a second clock frequency responsive to the identifying the lowest clock frequency and the highest clock frequency during the analysis period.
33. The method of claim 29 , wherein identifying sampling frequencies for performing the simulation of the clock gates and the gated-devices of the electronic circuitry design comprises:
identifying all clock frequencies during an analysis period; and
determining a least-common multiple clock frequency responsive to identifying all clock frequencies during the analysis period.
34. The method of claim 32 , wherein determining the second clock frequency responsive to the identifying the lowest clock frequency and the highest clock frequency during the analysis period comprises:
identifying a multiple of the lowest clock frequency that is the same or higher to the highest clock frequency; and
defining the second clock frequency responsive to identifying the multiple of the lowest clock frequency.