Transistors incorporating metal quantum dots into doped source and drain regions
Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.
1. A device, comprising:
a substrate having a first surface and a second surface opposite the first surface;
a gate;
a source region having a source contact between the first surface and the second surface of the substrate, the source region having a first surface that is coplanar with the first surface of the substrate, the source contact including a first conductive portion and a second conductive portion surrounded by the first conductive portion; and
a drain region having a drain contact between the first surface and the second surface of the substrate, the drain region having a first surface that is coplanar with the first surface of the substrate, the drain contact including a third conductive portion and a fourth conductive portion surrounded by the third conductive portion.
2. The device of claim 1 , wherein the gate is between the first surface of the substrate and the second surface of the substrate.
3. The device of claim 1 , wherein the gate has a first surface that is coplanar with the first surface of the substrate.
4. The device of claim 1 wherein the gate extends from the first surface of the substrate to a first depth, the source region extends from the first surface of the substrate to a second depth, the first depth being greater than the second depth.
5. The device of claim 4 wherein the drain region extends from the first surface of the substrate to a third depth, the first depth being greater than the third depth.
6. The device of claim 1 wherein the gate includes a plurality of U-shaped layers.
7. The device of claim 1 wherein the first conductive portion and the third conductive portion each include a U-shaped metal silicide layer.
8. A method, comprising:
forming a gate;
forming a source region having a source contact between a first surface and a second surface of a substrate that is opposite the first surface of the substrate, the source region having a first surface that is coplanar with the first surface of the substrate, the source contact including a U-shaped first conductive portion and a second conductive portion surrounded by the first conductive portion; and
forming a drain region having a drain contact between the first and second surfaces of the substrate, the drain region having a first surface that is coplanar with the first surface of the substrate, the drain contact including a U-shaped third conductive portion and a fourth conductive portion surrounded by the third conductive portion.
9. The method of claim 8 , further comprising forming the gate between the first surface of the substrate and the second surface of the substrate.
10. The method of claim 8 , further comprising forming a first surface of the gate coplanar with the first surface of the substrate.
11. The method of claim 8 , further comprising forming an opening for the gate from the first surface of the substrate to a first depth, and forming the gate in the opening.
12. The method of claim 11 , further comprising forming an opening for the source region extending from the first surface of the substrate to a second depth, the first depth being greater than the second depth.
13. A method, comprising:
forming a gate including a gate electrode between a first surface of a substrate and a second surface of the substrate, the gate being embedded in the substrate and having a first surface that is coplanar with the first surface of the substrate;
forming a source region having a source contact between the first and second surfaces of the substrate; and
forming a drain region having a drain contact between the first and second surfaces of the substrate and embedded in the drain region,
wherein the gate electrode, the source contact and the drain contact include a same conductive metal.
14. The method of claim 13 , wherein forming the gate includes forming an opening for the gate from the first surface of the substrate to a first depth and forming the gate in the opening.
15. The method of claim 14 , wherein forming the source region includes forming an opening for the source region from the first surface of the substrate to a second depth and wherein forming the drain region includes forming an opening for the drain region from the first surface of the substrate to a third depth, the first depth being greater than the second depth and the third depth.
16. The method of claim 13 , further comprising forming a U-shaped metal silicide layer in each of the source region and the drain region.
17. The method of claim 13 , further comprising forming an epitaxial channel prior to forming the gate, wherein the gate is formed over the epitaxial channel.
18. The method of claim 17 , wherein forming the gate further forming a gate dielectric, the gate dielectric contacting the epitaxial channel.
19. The method of claim 15 , further comprising depositing the conductive metal in each of the opening for the gate, the opening for the source region and the opening for the drain region.
20. The method of claim 19 , wherein the conductive metal includes tungsten, copper, silver, gold, or aluminum.