IP Library Granted Patent US 10,985,762
Granted Patent B2
US 10,985,762 · App. 16/240,357 · Granted Apr 20, 2021

Compensating for frequency variation of a crystal oscillator and related systems, methods and devices

Inventor: Arnel Tagatac (Lake Forest, CA)
Assignee: Microchip Technology Incorporated
H03L1/023H03B5/04H03B5/30
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Quick Facts
Patent No.
US 10,985,762
App. No.
16/240,357
Granted
Apr 20, 2021
Kind
B2
Abstract

Systems, methods, and devices of the present disclosure relate, generally, to compensating for frequency error of a reference signal supplied to a clock-tracking-loop due to temperature. Error characteristics of a crystal oscillator that supplies the reference signal are used to compensate for possible frequency errors. Other systems, methods and devices are disclosed.

Claims (69)

1. A method of configuring a clock-tracking-loop (CTL) for operation across a wide temperature range, the method comprising:

receiving one or more temperature measurements associated with a crystal oscillator providing a reference signal to—the CTL—;

selecting one of a number of pre-calibrated operational settings of the CTL, the number of precalibrated operational settings pre-calibrated responsive to one or more temperatures and one or more frequency error characteristics associated with the crystal oscillator; and

configuring the CTL to adjust an output signal of the CTL responsive to the selected pre-calibrated operational setting and the one or more temperature measurements.

2. The method of claim 1 , further comprising:

determining a frequency offset compensation responsive to at least one temperature measurement of the one or more temperature measurements and at least one frequency error characteristic of the one or more frequency error characteristics; and

determining at least one device parameter associated with the CTL responsive to the frequency offset compensation and one or more operational settings associated with the CTL.

3. The method of claim 2 , further comprising:

adjusting at least one operational setting of the one or more operational settings responsive to the frequency offset compensation; and

determining a device parameter for configuring the CTL responsive to the adjusted at least one operational setting.

4. The method of claim 3 , further comprising selecting the at least one frequency error characteristic responsive to a curve fit function that defines a frequency error characteristic versus temperature.

5. The method of claim 3 , further comprising:

searching a look-up-table for one or more temperature entries that match the at least one temperature measurement;

providing the at least one frequency error characteristic responsive to the search; and

taking an inverse of the at least one frequency error characteristic.

6. The method of claim 3 , further comprising:

searching a look-up-table for one or more temperature entries and one or more frequencies that match the at least one temperature measurement and the at least one operational setting, wherein the at least one operational setting corresponds to one or more frequencies of interest;

providing the at least one frequency error characteristic responsive to the search; and

taking an inverse of the at least one frequency error characteristic.

7. The method of claim 2 , further comprising:

adjusting a frequency of a feedback signal of the CTL responsive to the at least one device parameter, wherein the feedback signal corresponds to a first frequency of the output signal of the CTL;

generating a phase error signal responsive to the adjusted frequency of the feedback signal and the reference signal supplied by the crystal oscillator; and

providing the adjusted output signal responsive to the phase error signal, wherein the adjusted output signal has a second frequency.

8. The method of claim 7 , wherein the CTL is a phase-locked-loop and adjusting the frequency of the feedback signal comprises frequency dividing the feedback signal responsive to the device parameter.

9. The method of claim 7 , wherein the CTL is a delay-locked-loop and adjusting the frequency of the feedback signal comprises phase dividing the feedback signal responsive to the device parameter.

10. The method of claim 1 , further comprising calibrating the CTL for frequency variation for an expected use at room temperature.

11. The method of claim 10 , wherein calibrating the CTL for frequency variation for an expected use at room temperature comprises:

controlling the CTL to generate a test output signal having a test frequency responsive to a test device parameter, wherein the test device parameter is associated with a known output signal having a known frequency;

detecting a difference between test frequency of the test output signal and the known frequency of the known output signal; and

updating one or more settings associated with the CTL responsive to the detected difference.

12. The method of claim 11 , wherein the one or more settings are one or more operational settings used by a controller to configure the CTL to operate in one or more applications.

13. A control system for a clock-tracking-loop—(CTL)—, the control system comprising:

a temperature sensor configured to provide one or more temperature measurements associated with a crystal oscillator;

an error compensation circuitry configured to select one of a number of pre-calibrated operational settings of—the CTL—, the number of pre-calibrated operational settings pre-calibrated responsive to one or more temperatures and one or more determined frequency error characteristics of the crystal; and

a control circuitry configured to program the CTL to adjust an output signal of the CTL responsive to the selected pre-calibrated operational setting and the one or more temperature measurements.

14. The control system of claim 13 , wherein the error compensation circuitry is configured to determine a frequency offset compensation responsive to:

at least one temperature measurement of the one or more temperature measurements; and

at least one frequency error characteristic of the one or more determined frequency error characteristics.

15. The control system of claim 14 , wherein the error compensation circuitry is configured to select the at least one frequency error characteristic responsive to a curve fit function that defines a frequency error characteristic versus temperature.

16. The control system of claim 14 , wherein the error compensation circuitry is configured to:

search a look-up-table for one or more temperature entries that match the at least one temperature measurement;

provide the at least one frequency error characteristic responsive to the search; and

take an inverse of the at least one frequency error characteristic.

17. The control system of claim 14 , wherein the error compensation circuitry is configured to:

search a look-up-table for one or more temperature entries and one or more frequencies that match the at least one temperature measurement and at least one operational setting, wherein the at least one operational setting corresponds to one or more frequencies of interest;

provide the at least one frequency error characteristic responsive to the search; and

take an inverse of the at least one frequency error characteristic.

18. The control system of claim 14 , wherein the control circuitry is configured to determine at least one device parameter associated with the CTL responsive to the frequency offset compensation and one or more operational settings associated with the CTL.

19. The control system of claim 18 , wherein the control circuitry is configured to:

adjust at least one operational setting of the one or more operational settings responsive to the frequency offset compensation; and

determine a device parameter for configuring the CTL responsive to the adjusted at least one operational setting.

20. The control system of claim 13 , further comprising calibration circuitry configured to calibrate the CTL for frequency variation for an expected use at room temperature.

21. The control system of claim 20 , wherein the calibration circuitry is configured to calibrate the CTL for frequency variation for an expected use at room temperature by:

controlling the CTL to generate a test output signal having a test frequency responsive to a test device parameter, wherein the test device parameter is associated with a known output signal having a known frequency;

detecting a difference between test frequency of the test output signal and the known frequency of the known output signal; and

updating one or more settings associated with the CTL responsive to the detected difference.

22. The control system of claim 21 , wherein the one or more settings are one or more operational settings used by a controller to configure the CTL to operate in one or more applications.

23. A clock-tracking-loop system, comprising:

a clock-tracking-loop (CTL) configured to provide an output signal that tracks to a reference signal provided by a crystal oscillator responsive to one or more device settings; and

a control circuitry configured to provide one or more device settings to the CTL, the control circuitry comprising:

a temperature sensor configured to provide one or more temperature measurements associated with a crystal oscillator;

an error compensation circuitry configured to select one of a number of pre-calibrated operational settings of the CTL, the number of pre-calibrated operational settings pre-calibrated responsive to one or more temperatures and one or more determined frequency error characteristics of the crystal oscillator; and

a control circuitry configured to program the CTL to adjust an output signal of the CTL responsive to the selected pre-calibrated operational setting and the one or more temperature measurements, and

wherein the CTL is configured to provide the output signal that tracks to the reference signal by:

adjusting a frequency of a feedback signal of the CTL responsive to at least one device parameter, wherein the feedback signal corresponds to a first frequency of the output signal of the CTL;

generating a phase error signal responsive to the adjusted frequency of the feedback signal and the reference signal supplied by the crystal oscillator; and

providing the adjusted output signal responsive to the phase error signal, wherein the adjusted output signal has a second frequency.

24. The clock-tracking-loop system of claim 23 , wherein the CTL is a phase-locked-loop and adjusting the frequency of the feedback signal comprises frequency dividing the feedback signal responsive to the at least one device parameter.

25. The clock-tracking-loop system of claim 23 , wherein the CTL is a delay-locked-loop and adjusting the frequency of the feedback signal comprises phase dividing the feedback signal responsive to the at least one device parameter.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2019
From: TAGATAC, ARNEL
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 047907/0381 →