Three-dimensional ferroelectric memory devices including a backside gate electrode and methods of making same

1. A three-dimensional memory device, comprising:

alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart one from another by line trenches, wherein the line trenches laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction; and

line trench fill structures located in the line trenches, wherein each of the line trench fill structures comprises a respective set of memory stack structures and each set of memory stack structures comprises a respective row of discrete memory stack structures located in a respective one of the line trenches and arranged along the first horizontal direction, a backside gate dielectric that contacts each memory stack structure within the respective set of memory stack structures, and a backside gate electrode contacting the backside gate dielectric,

wherein each memory stack structure comprises a ferroelectric material layer, a front-side gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front-side gate dielectric and the backside gate dielectric; and

wherein each of the line trench fill structures comprises a laterally undulating dielectric rail contacting the backside gate electrode, laterally extending along the first horizontal direction, and including a laterally alternating sequence of bulbous regions and neck regions that have a lesser width along the second horizontal direction than the bulbous regions.

2. The three-dimensional memory device of claim 1 , wherein each of the ferroelectric material layers, the front-side gate dielectrics, and the vertical semiconductor channels vertically extends from a first horizontal plane including bottom surfaces of bottommost ones of the electrically conductive strips of the alternating stacks to a second horizontal plane including top surfaces of topmost ones of the electrically conductive strips of the alternating stacks.

3. The three-dimensional memory device of claim 1 , wherein each of the backside gate electrodes laterally extends along the first horizontal direction and is configured to apply a backside bias voltage to each of the vertical semiconductor channels within a respective one of the line trench fill structures.

4. The three-dimensional memory device of claim 1 , wherein:

each of the backside gate electrodes has a laterally undulating profile;

the ferroelectric material layers comprise hafnium oxide; and

the electrically conductive strips contacts sidewalls of the ferroelectric material layers.

5. The three-dimensional memory device of claim 1 , wherein the backside gate dielectric comprises a continuous layer that contacts each memory stack structure within the respective set of memory stack structures.

6. The three-dimensional memory device of claim 1 , wherein the backside gate electrode is laterally spaced from each memory stack structure within the respective set of memory stack structures by a lateral spacing that is the same as a thickness of the backside gate dielectric.

7. The three-dimensional memory device of claim 1 , wherein each of the ferroelectric material layers is in direct contact with a respective backside gate dielectric.

8. The three-dimensional memory device of claim 1 , wherein:

each of the front-side gate dielectrics is in direct contact with a respective gate dielectric; and

each backside gate dielectric is in direct contact with a respective plurality of ferroelectric material layers of the ferroelectric material layers of the three-dimensional memory device.

9. The three-dimensional memory device of claim 1 , wherein each backside gate dielectric is in direct contact with a respective plurality of vertical semiconductor channels of the vertical semiconductor channels of the three-dimensional memory device.

10. A three-dimensional memory device, comprising:

an alternating stack of insulator layers and electrically conductive layers and located over a top surface of a substrate;

a memory stack structure vertically extending through the alternating stack and comprising a ferroelectric material layer, a front-side gate dielectric contacting the ferroelectric material layer, and a vertical semiconductor channel contacting the front-side gate dielectric;

a backside gate dielectric contacting the vertical semiconductor channel;

a backside gate electrode contacting the backside gate dielectric;

a source region contacting a bottom end of the vertical semiconductor channel; and

a source electrode surrounding the source region, comprising a conductive material that is different from a material of the source region, contacting an annular bottom surface of the ferroelectric material layer, and located underneath the alternating stack.

11. The three-dimensional memory device of claim 10 , wherein:

the memory stack structure is located within an opening that extends through the alternating stack and has a generally cylindrical shape; and

each of the ferroelectric material layer, the front-side gate dielectric, the vertical semiconductor channel, and the backside gate dielectric has a respective generally annular cylindrical shape.

12. The three-dimensional memory device of claim 10 , wherein each of the ferroelectric material layer, the front-side gate dielectric, the vertical semiconductor channel, and the backside gate dielectric vertically extends from a first horizontal plane including a bottom surface of a bottommost one of the electrically conductive layers to a second horizontal plane including a top surface of topmost one of the electrically conductive layers.

13. The three-dimensional memory device of claim 10 , further comprising

a drain region contacting a top end of the vertical semiconductor channel.

14. The three-dimensional memory device of claim 13 , wherein:

the source region has a first annular shape and laterally surrounds the backside gate electrode; and

a bottom surface of the backside gate electrode contacts a top surface of a patterned conductive material layer that underlies the source electrode.

15. The three-dimensional memory device of claim 10 , wherein a top surface of the source electrode contacts a bottom surface of an insulating layer within the alternating stack.

16. The three-dimensional memory device of claim 10 , further comprising a conductive material layer contacting a bottom surface of the backside gate electrode.

17. The three-dimensional memory device of claim 16 , wherein the conductive material layer underlies the source region and the source electrode, and is vertically spaced from the source region by another insulating layer.

18. The three-dimensional memory device of claim 10 , further comprising a backside contact via structure vertically extending through the alternating stack and contacting the source electrode.