Automated speed ramp control of stepper motors
Automated speed ramp control of stepper motor acceleration and deceleration using direct memory access (DMA) and core independent peripherals (CIPs) comprises a numerically controlled oscillator (NCO) controlled through direct memory access (DMA) transfers of prescale values used in combination with a clock oscillator to generate clock pulses that are a function of the clock oscillator frequency and the prescale values. This automates changing the frequency of the NCO, thereby controlling steeper motor speed, without requiring computer processing unit (CPU) overhead. The DMA module is enabled during a first number of clock pulses for step speed acceleration, disabled during a second number of clock pulses for normal operation at full step speed, and then re-enabled during a third number of clock pulses for step speed deceleration. A table in memory may store and provide a plurality of acceleration and deceleration prescale values for DMA transfers to the NCO.
1. An apparatus for automated speed ramp control of stepper motor acceleration and deceleration, comprising:
an oscillator having an output;
a numerically controlled oscillator (NCO) having oscillator and prescale value inputs and an output providing clock pulses, wherein the NCO oscillator input is coupled to the oscillator output and a frequency of the clock pulses from the NCO is a function of a frequency from the oscillator and the prescale value;
a memory for storing a plurality of acceleration and deceleration prescale values; and
a direct memory access (DMA) control circuit coupled between the NCO prescale value input and the memory, and the output of the NCO, wherein the DMA control circuit comprises a DMA controller configured to provide the NCO with the acceleration prescale values from the memory for a first number of clock pulses, and to provide the NCO with the deceleration prescale values from the memory for a third number of clock pulses, wherein the DMA controller is inhibited by the DMA control circuit for a second number of clock pulses wherein the DMA control circuit further comprises:
a first counter for counting the first number of clock pulses;
a second counter for counting the second number of clock pulses;
a third counter for counting the third number of clock pulses; and
a multiplexer having a first input coupled to the NCO output, a second input coupled to a fixed logic level, an output coupled to the DMA controller and input selection controlled by the first, second and third counters;
wherein
the first counter controls the multiplexer to couple the first input to the output thereof during the first number of clock pulses,
the second counter controls the multiplexer to couple the second input to the output thereof during the second number of clock pulses, and
the third counter controls the multiplexer to couple the first input to the output thereof during the third number of clock pulses.
2. The apparatus according to claim 1 , further comprising a central processing unit (CPU) configured to provide input values to the first, second, and third counter.
3. The apparatus according to claim 2 , wherein the CPU is further configured to generate a reset for said DMA control circuit.
4. The apparatus according to claim 2 , wherein the first counter is configured to receive an acceleration count value as an input value from the CPU.
5. The apparatus according to claim 2 , wherein the second counter is configured to receive an maximum speed count value as an input value from the CPU.
6. The apparatus according to claim 2 , wherein the third counter is configured to receive an deceleration count value as an input value from the CPU.
7. The apparatus according to claim 2 , wherein the third counter is configured to generate an interrupt.
8. The apparatus according to claim 1 , wherein the fixed logic level is a logic zero.
9. The apparatus according to claim 1 , wherein the oscillator, NCO, memory and DMA control circuit are provided by a microcontroller.