Multi-modulus frequency dividers
Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include determining a common state for the MMD, wherein the MMD is configured to enter the common state regardless of a divisor value applied to the MMD. The method may further include receiving an integer value at the MMD. Further, the method may include setting the divisor value equal to the integer value. The method may also include receiving an input signal at a first frequency and generating an output signal at a second, lower frequency based on the divisor value. The method may also include receiving a second integer value at the MMD. The method may further include setting the divisor value equal to the second integer value in response to a detected current state of the MMD matching the common state for the MMD.
1. A method of operating a multi-modulus divider, the method comprising:
determining a common state for the multi-modulus divider (MMD), the MMD configured to enter the common state regardless of a divisor value applied to the MMD;
receiving a first integer value at the MMD;
setting the divisor value equal to the first integer value;
receiving an input signal at a first frequency;
generating an output signal at a second, lower frequency based on the divisor value;
receiving a second integer value at the MMD; and
setting the divisor value equal to the second integer value in response to a current state of the MMD matching the common state for the MMD.
2. The method of claim 1 , further comprising detecting the current state of the MMD.
3. The method of claim 2 , wherein detecting the current state of the MMD comprises sensing at least one signal within the MMD.
4. The method of claim 2 , further comprising:
comparing the current state of the MMD to the determined common state;
generating, via a first logic gate, a first digital signal in response to the current state matching the determined common state; and
generating, via the first logic gate, a second, different digital signal in response to the current state not matching the determined common state.
5. The method of claim 4 , further comprising generating, via a second logic gate, a third digital signal in response to receipt of at least one of the first digital signal and a reset signal, the third digital signal configured to enable the divisor value to be set equal to the second integer value.
6. The method of claim 1 , wherein the determining the common state for the MMD comprises determining the common state being 29 for two unit cells of the MMD.
7. The method of claim 1 , further comprising setting the divisor value equal to the first integer value in response to receipt of a reset signal.
8. A device, comprising:
a multi-modulus frequency divider (MMD) including a plurality of unit cells, each unit cell of the plurality configured to receive an input indicative of a divisor value of the MMD; and
a control circuit coupled to the MMD and configured to:
receive an integer value,
detect a state of the MMD; and
set the divisor value of the MMD equal to the integer value in response to the detected state of the MMD matching a common state for the MMD, the MMD configured to enter the common state regardless of a value of the divisor value.
9. The device of claim 8 , wherein the control circuit includes a state monitoring circuit coupled to the MMD and configured to detect the state of the MMD.
10. The device of claim 9 , wherein the state monitoring circuit includes an AND gate having a plurality of inputs coupled to the MMD.
11. The device of claim 10 , wherein the control circuit includes:
an OR gate configured to receive an output of the AND gate and a reset signal;
a first multiplexer configured to receive the integer value and a default divisor value;
a latch configured to receive an output of the OR gate and an output of the first multiplexer; and
a second multiplexer configured to receive an output of the latch and the default divisor value.
12. The device of claim 8 , further comprising:
a voltage controlled oscillator (VCO) having an output coupled to an input of the MMD; and
a processing unit having an input coupled to an output of the MMD and an output coupled to an input of the VCO.
13. The device of claim 8 , wherein the common state is 29 for two unit cells of the MMD.
14. A method of operating a multi-modulus divider, the method comprising:
receiving a default divisor value at the multi-modulus divider (MMD);
setting a divisor value of the MMD equal to the default divisor value;
receiving a generated divisor value at the MMD; and
setting the divisor value equal to the generated divisor value in response to a current state of the MMD matching a common state for the MMD, the MMD configured to enter the common state regardless of the divisor value loaded by the MMD.
15. The method of claim 14 , further comprising determining the common state for the MMD.
16. The method of claim 15 , wherein determining the common state for the MMD comprises identifying a state in which the MMD enters regardless of the divisor value.
17. The method of claim 14 , further comprising, for each state of the MMD, comparing the state of the MMD to the common state to determine if the state of the MMD matches the common state.
18. The method of claim 14 , wherein setting the divisor value equal to the generated divisor value in response to the current state of the MMD matching the common state comprises setting the divisor value equal to the generated divisor value in response to the current state of two unit cells of the MMD being 29.
19. The method of claim 14 , wherein setting the divisor value equal to the generated divisor value in response to the current state of the MMD matching the common state comprises setting the divisor value equal to the generated divisor value in response to the current state of the MMD matching the common state and the generated divisor value being equal to or greater than 32.
20. A device, comprising:
a cascaded multi-modulus frequency divider (MMD) configured to:
receive a divisor value;
receive a first signal at a first frequency; and
output a second signal at a second, reduced frequency based on the divisor value; and
a control circuit coupled to the MMD and configured to:
receive a generated divisor value; and
convey the generated divisor value to MMD for loading thereof as the divisor value in response to a detected state of the MMD matching a determined common state for the MMD, the MMD configured to enter the common state regardless of a value of the divisor value.