Self-timed processors implemented with multi-rail null convention logic and unate gates
There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.
1. A self-timed processor comprising:
a plurality of functional blocks comprising multi-rail null convention logic, each of the functional blocks to output one or more multi-rail data values that each alternate between a valid state and a null state, and
a global acknowledge tree to generate a global acknowledge signal provided to all of the plurality of functional blocks, wherein the global acknowledge signal switches to a null state when all of the one or more multi-rail data values output from all of the plurality of functional blocks are in the null state, wherein each of the plurality of functional blocks further comprises:
a register to receive the global acknowledge signal from the global acknowledge tree; and
combinatorial logic to output the one or more multi-rail data values to the register,
wherein the combinatorial logic of at least one of the plurality of functional blocks comprises one or more non-threshold, Boolean gates that include AND gates and OR gates.
2. The self-timed processor of claim 1 , wherein the Boolean gates are AND gates and OR gates.
3. The self-timed processor of claim 1 , wherein each of the plurality of functional blocks further comprises:
a local acknowledge tree to output a local acknowledge signal for the register; and
the global acknowledge tree to combine the local acknowledge signals into the global acknowledge signal.
4. The self-timed processor of claim 1 , wherein
the combinatorial logic of all of the plurality of functional blocks comprises one or more non-threshold, Boolean gates, which do not provide input completeness.
5. The self-timed processor of claim 4 , wherein
the registers included in the plurality of functional blocks comprise threshold gates.
6. The self-timed processor of claim 1 , wherein
the global acknowledge tree comprises gates that are threshold gates, and which provide input completeness.
7. A self-timed processor comprising:
a plurality of registers; and
a global acknowledge tree to generate a global acknowledge signal provided to all of the plurality of registers, wherein
two or more multi-rail null convention logic (NCL) data values output from a first one or more of the plurality of registers are combined by one or more non-threshold, Boolean gates of combinatorial logic to provide at least one multi-rail NCL input to a second one of the plurality of registers, wherein the two or more multi-rail NCL data values each alternate between a valid state and a null state, wherein the non-threshold, Boolean gates include AND gates and OR gates, and wherein the global acknowledge signal switches to a null state when all of the two or more NCL multi-rail values data output from all of the plurality of registers are in the null state.
8. The self-timed processor of claim 7 , wherein the Boolean gates are AND gates and OR gates.
9. The self-timed processor of claim 7 , further comprising:
a plurality of local acknowledge trees to each output a local acknowledge signal for each of the plurality of registers; and
the global acknowledge tree to combine the local acknowledge signals into the global acknowledge signal.
10. The self-timed processor of claim 7 , wherein
the combinatorial logic of all of the plurality of functional blocks comprises one or more non-threshold, Boolean gates, which do not provide input completeness.
11. The self-timed processor of claim 7 , wherein at least some of the plurality of registers comprise threshold gates.
12. The self-timed processor of claim 7 , wherein
the global acknowledge tree comprises gates that are threshold gates, and which provide input completeness.
13. A method of processing data within a self-timed processor, comprising:
combining two or more multi-rail null convention logic (NCL) data values output from a first one or more of a plurality of registers using one or more non-threshold, Boolean gates to provide at least one multi-rail NCL input to a second one of the plurality of registers, wherein the non-threshold, Boolean gates include AND gates and OR gates, wherein the two or more multi-rail NCL data values each alternate between a valid state and a null state, and
generating a global acknowledge signal provided to all of the plurality of registers, and
switching the global acknowledge signal a null state when all of the two or more NCL multi-rail values data output from all of the plurality of registers are in the null state.
14. The method of claim 13 , wherein the Boolean gates are AND gates and OR gates.
15. The method of claim 13 , further comprising:
combining two or more multi-rail null convention logic (NCL) data values output from each of the plurality of registers using one or more non-threshold, Boolean gates to provide at least one multi-rail NCL input to a second one of the plurality of registers; and
wherein the non-threshold, Boolean gates do not provide input completeness.
16. The method of claim 13 , further comprising:
outputting a local acknowledge signal for each register; and
combining the local acknowledge signals into the global acknowledge signal.
17. The method of claim 16 , wherein
generating the global acknowledge signal is performed by an acknowledge tree comprising gates that are threshold gates, and which provide input completeness.