Multi-bit dot product engine
A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors T 1 and T 2 , where T 1 is controlled by the value held in the associated memory cell and T 2 is controlled by a row-dedicated source (v in ) for each row, the combination of the T 1 and T 2 transistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2 (M-1) , . . . Rmax, where Rmax is the resistance of the least significant cell in each row.
1. A multi-bit dot product engine-based memory for carrying out vector-based dot products, comprising:
a matrix of memory cells having M rows (M- 1 , M- 2 , . . . 0) and N columns (N- 1 , N- 2 , . . . 0), each memory cell (C) in each of the rows ((C N-1 , C N-2 , . . . , C 0 ) M-1 , (C N-1 , C N-2 , . . . , C 0 ) M-2 , . . . (C N-1 , C N-2 , . . . , C 0 ) 0 ) holding a value and having dedicated read transistors T 1 and T 2 , where T 1 is controlled by the value held in the associated memory cell and T 2 is controlled by a row-dedicated read word line RWL i (RWL M-1 , RWL M-2 , . . . RWL 0 ), the combination of the T 1 and T 2 transistors for each cell selectively (i) couple a row-dedicated source (v in ) for each row ((v in ) M-1 , (v in ) M-2 , . . . (v in ) 0 ) with a column-dedicated read bit line (RBL) for each column (RBL N-1 , RBL N-2 , . . . RBL 0 ) for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column (RBL N-1 , RBL N-2 , . . . RBL 0 ) for a memory read operation, where total resistance of the T 1 and T 2 transistors (R) for each cell (R N-1 , R N-2 , . . . , R 0 ) in each row (M- 1 , M- 2 , . . . 0) is based on Rmax/2 (M-1) , Rmax/2 (M-2) , . . . Rmax, where Rmax is the resistance of the least significant cell in each row and where current in each RBL (I RBL ) for each column ((I RBL ) N-1 , (I RBL ) N-2 , . . . (I RBL ) 0 ) is summed as I out ; and
a sensing circuit coupled to the matrix of memory cells and adapted to selectively (i) receive and convert the current I out to a digital value representing an output of the vector-based dot product, or (ii) sense voltage at each of the RBLs (RBL N-1 , RBL N-2 , . . . RBL 0 ) to read value of the corresponding cells.
2. The multi-bit dot product engine-based memory of claim 1 , wherein the sensing circuit is based on a sense resistor generating an analog voltage and an analog-to-digital converter generating a digital representation of the analog voltage.
3. The multi-bit dot product engine-based memory of claim 1 , wherein the sensing circuit includes an operational amplifier (op-amp) generating an analog voltage and an analog-to-digital converter generating a digital representation of the analog voltage.
4. The multi-bit dot product engine-based memory of claim 3 , wherein the op-amp receives the analog current I out at its negative terminal, a reference voltage (V pos ) at its positive terminal and a feedback resistor R f between its output and the negative terminal, wherein the op-amp's output is Vout=−I out ·R f +V pos .
5. The multi-bit dot product engine-based memory of claim 1 , wherein R is adjusted for each cell based on adjusting conductances of corresponding T 1 and T 2 .
6. The multi-bit dot product engine-based memory of claim 5 , wherein the conductances are adjusted for each cell based on adjusting threshold voltages of corresponding T 1 and T 2 .
7. The multi-bit dot product engine-based memory of claim 5 , wherein the conductances are adjusted for each cell based on adjusting sizes of corresponding T 1 and T 2 .
8. A multi-bit dot product engine-based memory for carrying out vector-based dot products, comprising:
a matrix of memory cells having M rows (M- 1 , M- 2 , . . . 0) and N columns (N- 1 , N- 2 , . . . 0), each memory cell (C) in each of the rows ((C N-1 , C N-2 , . . . , C 0 ) M-1 , (C N-1 , C N-2 , . . . , C 0 ) M-2 , . . . (C N-1 , C N-2 , . . . , C 0 ) 0 ) holding a value and having dedicated read transistors T 1 and T 2 , where T 1 is controlled by the value held in the associated memory cell and T 2 is controlled by a row-dedicated source (v in ) for each row ((v in ) M-1 , (v in ) M-2 , . . . (v in ) 0 ), the combination of the T 1 and T 2 transistors for each cell selectively (i) couple a reference voltage (V bias ) with a column-dedicated read bit line (RBL) for each column (RBL N-1 , RBL N-2 , . . . RBL 0 ) for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column (RBL N-1 , RBL N-2 , . . . RBL 0 ) for a memory read operation, where total resistance of the T 1 and T 2 transistors (R) for each cell (R N-1 , R N-2 , . . . , R 0 ) in each row (M- 1 , M- 2 , . . . 0) is based on Rmax/2 (M-1) , Rmax/2 (M-2) , . . . Rmax, where Rmax is the resistance of the least significant cell in each row and where current in each RBL (I RBL ) for each column ((I RBL ) N-1 , (I RBL ) N-2 , . . . (I RBL ) 0 ) is summed as I out ; and
a sensing circuit coupled to the matrix of memory cells and adapted to selectively (i) receive and convert the current I out to a digital value representing an output of the vector-based dot product, or (ii) sense voltage at each of the RBLs (RBL N-1 , RBL N-2 , . . . RBL 0 ) to read value of the corresponding cells.
9. The multi-bit dot product engine-based memory of claim 8 , wherein the sensing circuit is based on a sense resistor generating an analog voltage and an analog-to-digital converter generating a digital representation of the analog voltage.
10. The multi-bit dot product engine-based memory of claim 8 , wherein the sensing circuit includes an operational amplifier (op-amp) generating an analog voltage and an analog-to-digital converter generating a digital representation of the analog voltage.
11. The multi-bit dot product engine-based memory of claim 10 , wherein the op-amp receives the analog current I out at its negative terminal, a reference voltage (V pos ) at its positive terminal and a feedback resistor R f between its output and the negative terminal, wherein the op-amp's output is Vout=−I out ·R f +V pos .
12. The multi-bit dot product engine-based memory of claim 8 , wherein R is adjusted for each cell based on adjusting conductances of corresponding T 1 and T 2 .
13. The multi-bit dot product engine-based memory of claim 12 , wherein the conductances are adjusted for each cell based on adjusting threshold voltages of corresponding T 1 and T 2 .
14. The multi-bit dot product engine-based memory of claim 12 , wherein the conductances are adjusted for each cell based on adjusting sizes of corresponding T 1 and T 2 .
15. A method of obtaining an in-memory vector-based dot product, comprising:
providing a matrix of memory cells having M rows (M- 1 , M- 2 , . . . 0) and N columns (N- 1 , N- 2 , . . . 0), each memory cell (C) in each of the rows ((C N-1 , C N-2 , . . . , C 0 ) M-1 , (C N-1 , C N-2 , . . . , C 0 ) M-2 , . . . (C N-1 , C N-2 , . . . , C 0 ) 0 ) holding a value and having dedicated read transistors T 1 and T 2 , where T 1 is controlled by the value held in the associated memory cell and T 2 is controlled by a row-dedicated source (v in ) for each row ((v in ) M-1 , (v in ) M-2 , . . . (v in ) 0 ), the combination of the T 1 and T 2 transistors for each cell selectively (i) couple a reference voltage (V bias ) with a column-dedicated read bit line (RBL) for each column (RBL N-1 , RBL N-2 , . . . RBL 0 ) for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column (RBL N-1 , RBL N-2 , . . . RBL 0 ) for a memory read operation, where total resistance of the T 1 and T 2 transistors (R) for each cell (R N-1 , R N-2 , . . . , R 0 ) in each row (M- 1 , M- 2 , . . . 0) is based on Rmax/2 (M-1) , Rmax/2 (M-2) , . . . Rmax, where Rmax is the resistance of the least significant cell in each row and where current in each RBL (I RBL ) for each column ((I RBL ) N-1 , (I RBL ) N-2 , . . . (I RBL ) 0 ) is summed as I out ; and
selectively (i) receiving and converting the current I out to a digital value representing an output of the vector-based dot product, or (ii) sensing voltage at each of the RBLs (RBL N-1 , RBL N-2 , . . . RBL 0 ) to read value of the corresponding cells.
16. The method of claim 15 , wherein the sensing circuit is based on a sense resistor generating an analog voltage and an analog-to-digital converter generating a digital representation of the analog voltage.
17. The method of claim 15 , wherein the sensing circuit includes an operational amplifier (op-amp) generating an analog voltage and an analog-to-digital converter generating a digital representation of the analog voltage.
18. The method of claim 17 , wherein the op-amp receives the analog current I out at its negative terminal, a reference voltage (V pos ) at its positive terminal and a feedback resistor R f between its output and the negative terminal, wherein the op-amp's output is Vout=−I out ·R f +V pos .
19. The method of claim 15 , wherein R is adjusted for each cell based on adjusting conductances of corresponding T 1 and T 2 .
20. The method of claim 19 , wherein the conductances are adjusted for each cell based on adjusting one or more of threshold voltages and sizes of corresponding T 1 and T 2 .