Semicondutor device
[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed. [Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j-1th sub memory cell.
1. A semiconductor device comprising:
a memory cell including first to cth sub memory cells (c is a natural number greater than or equal to 2),
wherein a jth sub memory cell includes a transistor and a capacitor (j is a natural number of 1 to c),
wherein a semiconductor layer in the transistor includes an oxide semiconductor,
wherein one of terminals of the capacitor is electrically connected to one of a source electrode and a drain electrode of the transistor,
wherein, when j≥2, the jth sub memory cell is arranged over a j-1th sub memory cell, and
wherein a bit line is electrically connected to the jth sub memory cell and the j-1th sub memory cell.
2. The semiconductor device according to claim 1 ,
wherein the transistor has an off-state current lower than or equal to 10 zA per micrometer of channel width at room temperature.
3. The semiconductor device according to claim 1 ,
wherein the bit line includes a plug.
4. The semiconductor device according to claim 1 ,
wherein the memory cell is provided over a semiconductor substrate, and
wherein the bit line extends in a direction perpendicular or substantially perpendicular to the semiconductor substrate.
5. The semiconductor device according to claim 1 ,
wherein the bit line extends in a direction in which a layer including the j-1th sub memory cell and a layer including the jth sub memory cell are stacked.
6. The semiconductor device according to claim 1 ,
wherein the memory cell is provided over a peripheral circuit including a transistor including silicon in a semiconductor layer.
7. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor includes In, Ga, and Zn.
8. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor includes a crystal region, and
wherein the crystal region includes a crystal in which a c-axis is aligned in a direction perpendicular or substantially perpendicular to a surface of the oxide semiconductor.
9. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor includes a region in which a hydrogen concentration is lower than 5×10 18 atoms/cm 3 .
10. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor is highly purified.
11. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor is intrinsic or substantially intrinsic.
12. A semiconductor device comprising:
a memory cell including first to cth sub memory cells (c is a natural number greater than or equal to 2),
wherein a jth sub memory cell includes a first transistor, a second transistor, and a capacitor (j is a natural number of 1 to c),
wherein a first semiconductor layer in the first transistor and a second semiconductor layer in the second transistor include an oxide semiconductor,
wherein one of terminals of the capacitor is electrically connected to a gate electrode of the second transistor,
wherein the gate electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the first transistor,
wherein, when j≥2, the jth sub memory cell is arranged over a j-1th sub memory cell, and
wherein a bit line is electrically connected to the jth sub memory cell and the j-1th sub memory cell.
13. The semiconductor device according to claim 12 ,
wherein the first transistor has an off-state current lower than or equal to 10 zA per micrometer of channel width at room temperature.
14. The semiconductor device according to claim 12 ,
wherein the bit line includes a plug.
15. The semiconductor device according to claim 12 ,
wherein the memory cell is provided over a semiconductor substrate, and
wherein the bit line extends in a direction perpendicular or substantially perpendicular to the semiconductor substrate.
16. The semiconductor device according to claim 12 ,
wherein the bit line extends in a direction in which a layer including the j-1th sub memory cell and a layer including the jth sub memory cell are stacked.
17. The semiconductor device according to claim 12 ,
wherein the memory cell is provided over a peripheral circuit including a transistor including silicon in a semiconductor layer.
18. The semiconductor device according to claim 12 ,
wherein the oxide semiconductor includes In, Ga, and Zn.
19. The semiconductor device according to claim 12 ,
wherein the oxide semiconductor includes a crystal region, and
wherein the crystal region includes a crystal in which a c-axis is aligned in a direction perpendicular or substantially perpendicular to a surface of the oxide semiconductor.
20. The semiconductor device according to claim 12 ,
wherein the oxide semiconductor includes a region in which a hydrogen concentration is lower than 5×10 18 atoms/cm 3 .
21. The semiconductor device according to claim 12 ,
wherein the oxide semiconductor is highly purified.
22. The semiconductor device according to claim 12 ,
wherein the oxide semiconductor is intrinsic or substantially intrinsic.