IP Library Granted Patent US 12,538,523
Granted Patent B2
US 12,538,523 · App. 17/634,564 · Granted Jan 27, 2026

Semiconductor device comprising transitor, capacitor and plug

Inventors: Shunpei Yamazaki (Setagaya, JP); Yoshinori Ando (Atsugi, JP); Ryota Hodo (Atsugi, JP); Takashi Hirose (Yokohama, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10D30/6755H01L23/5226H01L23/5283H10B12/30
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,538,523
App. No.
17/634,564
Granted
Jan 27, 2026
Kind
B2
Abstract

A semiconductor device with little characteristic variation is provided. A transistor includes an oxide semiconductor; a first conductor and a second conductor over the oxide semiconductor; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator that is positioned over the first insulator and the second insulator and provided with a first opening overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned over the oxide semiconductor and between the first conductor and the second conductor; and a third conductor over the fourth insulator. A capacitor includes the second conductor; the third insulator provided with a second opening reaching the second conductor; a fifth insulator positioned inside the second opening; and a fourth conductor over the fifth insulator. A plug is positioned to penetrate the first insulator, the third insulator, the first conductor, and the oxide semiconductor. The plug is electrically connected to the first conductor. The first insulator and the second insulator are each formed using a metal oxide including an amorphous structure.

Claims (88)

1 . A semiconductor device comprising:

a transistor;

a capacitor; and

a plug,

wherein the transistor comprises an oxide semiconductor; a first conductor and a second conductor over the oxide semiconductor; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator that is positioned over the first insulator and the second insulator and provided with a first opening overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned over the oxide semiconductor and between the first conductor and the second conductor; and a third conductor over the fourth insulator,

wherein the capacitor comprises the second conductor; the third insulator provided with a second opening reaching the second conductor; a fifth insulator positioned inside the second opening; and a fourth conductor over the fifth insulator,

wherein the fifth insulator is in contact with a top surface of the second conductor,

wherein the plug is positioned to penetrate the first insulator, the third insulator, the first conductor, and the oxide semiconductor,

wherein the plug is electrically connected to the first conductor, and

wherein the first insulator and the second insulator are each formed using a metal oxide comprising an amorphous structure.

2 . The semiconductor device according to claim 1 ,

wherein the metal oxide is AlO x (x is a given number greater than 0).

3 . A semiconductor device comprising:

a transistor;

a capacitor; and

a plug,

wherein the transistor comprises an oxide semiconductor; a first conductor and a second conductor over the oxide semiconductor; a first insulator that covers the first conductor and the second conductor and is provided with a first opening overlapping with a region between the first conductor and the second conductor; a second insulator that is positioned over the first insulator and provided with a second opening overlapping with the region between the first conductor and the second conductor; a third insulator positioned over the oxide semiconductor and between the first conductor and the second conductor; and a third conductor over the third insulator,

wherein the capacitor comprises the second conductor; the first insulator and the second insulator that are provided with a third opening reaching the second conductor; a fourth insulator positioned inside the third opening; and a fourth conductor over the fourth insulator,

wherein the fourth insulator is in contact with a top surface of the second conductor,

wherein the plug is positioned to penetrate the first insulator, the second insulator, the first conductor, and the oxide semiconductor,

wherein the plug is electrically connected to the first conductor, and

wherein the first insulator is formed using a metal oxide comprising an amorphous structure.

4 . The semiconductor device according to claim 3 ,

wherein the metal oxide is AlO x (x is a given number greater than 0).

5 . A semiconductor device comprising:

a transistor;

a capacitor; and

a plug,

wherein the transistor comprises an oxide semiconductor; a first conductor and a second conductor over the oxide semiconductor; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator that covers the first insulator and the second insulator and is provided with a first opening overlapping with a region between the first conductor and the second conductor; a fourth insulator that is positioned over the third insulator and provided with a second opening overlapping with the region between the first conductor and the second conductor; a fifth insulator positioned over the oxide semiconductor and in the region between the first conductor and the second conductor; and a third conductor over the fifth insulator,

wherein the capacitor comprises the second conductor; the second insulator, the third insulator, and the fourth insulator that are provided with a third opening reaching the second conductor; a sixth insulator positioned inside the third opening; and a fourth conductor over the sixth insulator,

wherein the sixth insulator is in contact with a top surface of the second conductor,

wherein the plug is positioned to penetrate the first insulator, the third insulator, the fourth insulator, the first conductor, and the oxide semiconductor,

wherein the plug is electrically connected to the first conductor, and

wherein the first insulator, the second insulator, and the third insulator are each formed using a metal oxide comprising an amorphous structure.

6 . The semiconductor device according to claim 5 , further comprising:

a seventh insulator; and

an eighth insulator,

wherein the seventh insulator is positioned under the oxide semiconductor,

wherein the eighth insulator is in contact with a top surface of the fourth insulator, a top surface of the third conductor, and a top surface of the fourth conductor, and

wherein the seventh insulator and the eighth insulator are each formed using a metal oxide comprising an amorphous structure.

7 . The semiconductor device according to claim 6 , further comprising a ninth insulator,

wherein the ninth insulator covers the eighth insulator and is in contact with a top surface of the seventh insulator in a region not overlapping with the fifth insulator, and

wherein the ninth insulator is formed using a metal oxide comprising an amorphous structure.

8 . The semiconductor device according to claim 7 , further comprising:

a tenth insulator; and

an eleventh insulator,

wherein the tenth insulator is in contact with a lower surface of the seventh insulator,

wherein the eleventh insulator is in contact with a top surface of the ninth insulator, and

wherein the tenth insulator and the eleventh insulator are each formed using silicon nitride.

9 . The semiconductor device according to claim 5 , further comprising:

a first nitride insulator; and

a second nitride insulator,

wherein the first nitride insulator is positioned between the first insulator and the third insulator,

wherein the second nitride insulator is positioned between the second insulator and the third insulator, and

wherein the first nitride insulator and the second nitride insulator are each formed using silicon nitride.

10 . The semiconductor device according to claim 5 ,

wherein a top surface of the first insulator and a top surface of the second insulator are in contact with the third insulator.

11 . The semiconductor device according to claim 5 ,

wherein the metal oxide is AlO x (x is a given number greater than 0).

12 . A semiconductor device comprising:

a first insulating layer;

a second insulating layer;

a first memory cell; and

a second memory cell,

wherein the first memory cell comprises a first transistor, a first capacitor, and a first plug,

wherein the first transistor comprises a first oxide semiconductor; a first conductor and a second conductor over the first oxide semiconductor; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator that is positioned over the first insulator and the second insulator and provided with a first opening overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned over the first oxide semiconductor and between the first conductor and the second conductor; and a third conductor over the fourth insulator,

wherein the first capacitor comprises the second conductor; the third insulator provided with a second opening reaching the second conductor; a fifth insulator positioned inside the second opening; and a fourth conductor over the fifth insulator,

wherein the fifth insulator is in contact with a top surface of the second conductor,

wherein the first plug is positioned to penetrate the first insulator, the third insulator, the first conductor, and the first oxide semiconductor,

wherein the first plug is electrically connected to the first conductor,

wherein the second memory cell comprises a second transistor, a second capacitor, and a second plug,

wherein the second transistor comprises a second oxide semiconductor; a fifth conductor and a sixth conductor over the second oxide semiconductor; a sixth insulator over the fifth conductor; a seventh insulator over the sixth conductor; an eighth insulator that is positioned over the sixth insulator and the seventh insulator and provided with a third opening overlapping with a region between the fifth conductor and the sixth conductor; a ninth insulator positioned over the second oxide semiconductor and between the fifth conductor and the sixth conductor; and a seventh conductor over the ninth insulator,

wherein the second capacitor comprises the sixth conductor; the eighth insulator provided with a fourth opening reaching the sixth conductor; a tenth insulator positioned inside the fourth opening; and an eighth conductor over the tenth insulator,

wherein the tenth insulator is in contact with a top surface of the sixth conductor,

wherein the second plug is positioned to penetrate the sixth insulator, the ninth insulator, the fifth conductor, and the second oxide semiconductor,

wherein the second plug is electrically connected to the fifth conductor,

wherein the first memory cell is provided over the first insulating layer,

wherein the second memory cell is provided over the first memory cell,

wherein a top surface of the first plug is electrically connected to the second plug,

wherein the second insulating layer is positioned to cover the first memory cell and the second memory cell, and

wherein the second insulating layer is in contact with part of a top surface of the first insulating layer in a region not overlapping with the first oxide semiconductor and the second oxide semiconductor.

13 . The semiconductor device according to claim 12 ,

wherein the first insulating layer comprises an eleventh insulator and a twelfth insulator over the eleventh insulator,

wherein the second insulating layer comprises a thirteenth insulator and a fourteenth insulator over the thirteenth insulator,

wherein the eleventh insulator and the thirteenth insulator each comprise silicon nitride, and

wherein the twelfth insulator and the fourteenth insulator are each formed using a metal oxide comprising an amorphous structure.

14 . The semiconductor device according to claim 13 ,

wherein the metal oxide is AlO x (x is a given number greater than 0).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2022
From: YAMAZAKI, SHUNPEI; ANDO, YOSHINORI; HODO, RYOTA; HIROSE, TAKASHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 058986/0291 →
Priority Claims (1)
JP 2019-158456 · Aug 30, 2019 · national
Continuity (1)
Related Publication 20220278235A1 · Sep 1, 2022
References Cited (39)
US 8837202B2 · Takemura · 2014 [cited by applicant]
US 8932903B2 · Sato et al. · 2015 [cited by applicant]
US 9142681B2 · Watanabe et al. · 2015 [cited by applicant]
US 9384816B2 · Takemura · 2016 [cited by applicant]
US 9825042B2 · Takemura · 2017 [cited by applicant]
US 9905516B2 · Watanabe et al. · 2018 [cited by applicant]
US 9917207B2 · Yamazaki · 2018 [cited by applicant]
US 10593683B2 · Atsumi et al. · 2020 [cited by applicant]
US 10784284B2 · Yamazaki · 2020 [cited by applicant]
US 10923477B2 · Yamazaki et al. · 2021 [cited by applicant]
US 11114449B2 · Atsumi et al. · 2021 [cited by applicant]
US 11164871B2 · Matsuzaki et al. · 2021 [cited by applicant]
US 11271013B2 · Yamazaki · 2022 [cited by applicant]
US 20130075735A1 · Watanabe et al. · 2013 [cited by applicant]
US 20150255139A1 · Atsumi et al. · 2015 [cited by applicant]
US 20160300952A1 · Toriumi · 2016 [cited by examiner]
US 20170309752A1 · Yamazaki · 2017 [cited by examiner]
US 20180061920A1 · Son et al. · 2018 [cited by applicant]
US 20180138183A1 · Lin · 2018 [cited by examiner]
US 20200203345A1 · Matsuzaki et al. · 2020 [cited by applicant]
US 20210175235A1 · Yamazaki et al. · 2021 [cited by applicant]
US 20210398988A1 · Atsumi et al. · 2021 [cited by applicant]
DE 112018000887 · 2019 [cited by applicant]
JP 2011151383A · 2011 [cited by applicant]
JP 2012119048A · 2012 [cited by applicant]
JP 2012257187A · 2012 [cited by applicant]
JP 2013084941A · 2013 [cited by applicant]
JP 2015181159A · 2015 [cited by applicant]
JP 2017098545A · 2017 [cited by applicant]
JP 2017120896A · 2017 [cited by applicant]
JP 2018133570A · 2018 [cited by applicant]
JP 2018206828A · 2018 [cited by applicant]
JP 2019096856A · 2019 [cited by applicant]
WO WO2017081579 · 2017 [cited by applicant]
WO WO2018150292 · 2018 [cited by applicant]
WO WO2019048987 · 2019 [cited by applicant]
German Office Action (Application No. 112020004134.4) Dated Aug. 21, 2024. [cited by applicant]
International Search Report (Application No. PCT/IB2020/057714) Dated Nov. 17, 2020. [cited by applicant]
Written Opinion (Application No. PCT/IB2020/057714) Dated Nov. 17, 2020. [cited by applicant]