Tap, counter storing value of serial access by communication circuitry
The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
1. Communication circuitry comprising:
(a) a test data in input, a bi-directional test mode select terminal, a test clock input, and a test data out output;
(b) test access port circuitry including test controller circuitry coupled to the test mode select terminal and the test clock input;
(c) serial communication circuitry separate from the test access port circuitry, the serial communication circuitry having a serially accessible register through the bi-directional test mode select terminal; and
(d) a counter operable to store a value corresponding to repetition of a serial access by the serial communication circuitry.
2. The communication circuitry of claim 1 in which the test access port circuitry includes:
an instruction register having an input coupled to the test data in input, control inputs coupled to state outputs of the test controller circuitry, parallel outputs, and a data output;
a data register having an input coupled to the test data in input, control inputs coupled to the state outputs, parallel outputs and parallel inputs, and a data output; and
multiplexer circuitry having data inputs coupled to the data outputs of the instruction register and the data register, having a control input coupled to the state outputs, and a data output coupled to the test data out output.
3. The communication circuitry of claim 1 including an integrated circuit containing the test data in input, the bi-directional test mode select terminal, the test clock input, the test data out output, the test access port circuitry, the serial communication circuitry, and the counter.
4. The communication circuitry of claim 1 in which the test controller circuitry has four state output bits defining sixteen states.
5. The communication circuitry of claim 1 in which the test controller circuitry has four state output bits defining a Test Logic Reset state, a Run Test/Idle state, a Select-DR state, and a Select-IR state.
6. The communication circuitry of claim 1 in which the test controller circuitry has four state output bits defining a Run Test/Idle state, a Shift-DR state, a Pause-DR state, a Shift-IR state, and a Pause-IR state.
7. The communication circuitry of claim 1 in which the counter has an input coupled to the test data in input and a data output coupled to the test data out output.