Device/health of line (HOL) aware eBeam based overlay (EBO OVL) structure

1. A method, comprising:

generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule;

simulating a worst case process margin for the generated device layout of the EBO OVL structure;

enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure; and

breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

2. The method of claim 1 , further comprising performing a health of line (HOL) test of a semiconductor device using the generated OVL measurement layout of the EBO OVL structure.

3. The method of claim 1 , further comprising generating a systematic staircase device aware eBeam based overlay (EBO) structure based on the generated OVL measurement layout of the EBO OVL structure.

4. The method of claim 1 , wherein the worst case process margin is simulated by determining a number of FINs and an etch loading effect for the generated device layout of the EBO OVL structure.

5. The method of claim 4 , further comprising performing adjustments to the number of FINs and the etch loading effect based on the simulated worst case process margin.

6. The method of claim 1 , wherein the EBO OVL structure is a device based EBO macro.

7. The method of claim 1 , wherein the breaking the plurality of design rules for the enabled plurality of devices of the EBO OVL structure comprises breaking at least one of a dummy gate region (PC) design rule, a single diffusion break (RB) design rule, and a fin cut layer (RC) design rule.

8. A method, comprising:

generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule;

simulating a worst case process margin for the generated device layout of the EBO OVL structure;

enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure;

breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure;

performing a health of line (HOL) test of a semiconductor device using the generated OVL measurement layout of the EBO OVL structure; and

generating a systematic staircase device aware eBeam based overlay (EBO) structure based on the generated OVL measurement layout of the EBO OVL structure,

wherein the EBO OVL structure is on a scribe line of the semiconductor device.

9. The method of claim 8 , wherein the worst case process margin is simulated by determining a number of FINs and an etch loading effect for the generated device layout of the EBO OVL structure.

10. The method of claim 9 , further comprising performing adjustments to the number of FINs and the etch loading effect based on the simulated worst case process margin.

11. The method of claim 8 , wherein the EBO OVL structure is a device based EBO macro.

12. The method of claim 8 , wherein the breaking the plurality of design rules for the enabled plurality of devices of the EBO OVL structure comprises breaking at least one of a dummy gate region (PC) design rule, a single diffusion break (RB) design rule, and a fin cut layer (RC) design rule.

13. The method of claim 8 , the EBO OVL structure is an active device of the semiconductor device.

14. The method of claim 8 , wherein the HOL test is used to extract open/short performance of the semiconductor device.