Integrated circuit structures
Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
1. A device structure, comprising:
a body, comprising a monocrystalline semiconductor material, adjacent to an isolation dielectric;
a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
a source and a drain coupled to the body on opposite sides of the gate stack;
a front-side interconnect metallization layer coupled to at least one of the source, drain, or gate electrode; and
a back-side device layer over a back-side surface of the body, opposite the front-side interconnect metallization layer, wherein the back-side device layer comprises a second semiconductor material having a different composition than that of the body; and
a back-side device terminal electrically coupled to the back-side device layer, wherein:
the structure comprises a first field effect transistor (FET) stacked over a second FET;
the second semiconductor material is monocrystalline;
a second gate stack is coupled to the second semiconductor material; and
the back-side device terminal further comprises a source or a drain of the second FET, which is coupled to the second semiconductor material.
2. The structure of claim 1 , wherein:
the monocrystalline semiconductor material comprises a first Group IV or Group III-V semiconductor; and
the second semiconductor material comprises a second Group IV or Group III-V semiconductor.
3. The structure of claim 1 , further comprising:
a back-side interconnect metallization layer coupled to the back-side device terminal, wherein
the body and the back-side device layer are located between the front-side interconnect metallization layer and the back-side interconnect metallization layer.
4. The structure of claim 1 , wherein the back-side device terminal is in contact with one of the source or drain of the FET.
5. The structure of claim 1 , wherein
the back-side interconnect metallization layer has a different composition than the front-side interconnect metallization layer.
6. The structure of claim 5 , wherein:
the front-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the back-side interconnect metallization layer, or the back-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the front-side interconnect metallization layer.
7. The IC structure of claim 6 , wherein the front-side interconnect metallization layer comprises one or more of Ru, Rh, Pd, Jr, Pt, Au, W, Cr, or Co, and the back-side interconnect metallization layer comprises Cu.
8. A device structure, comprising:
a body, comprising a monocrystalline semiconductor material, adjacent to an isolation dielectric;
a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
a source and a drain coupled to the body on opposite sides of the gate stack;
a front-side interconnect metallization layer coupled to at least one of the source, drain, or gate electrode; and
a back-side device layer over a back-side surface of the body, opposite the front-side interconnect metallization layer, wherein the back-side device layer comprises a second semiconductor material having a different composition than that of the body; and
a back-side device terminal electrically coupled to the back-side device layer, wherein:
the structure comprises a field effect transistor (FET) stacked over a thin film transistor (TFT);
the second semiconductor material is polycrystalline or amorphous;
a second gate stack is coupled to the second semiconductor material; and
the back-side device terminal further comprises a source or drain of the TFT, which is coupled to the second semiconductor material.
9. An integrated circuit (IC) structure, comprising:
a transistor body adjacent to a field isolation dielectric, the transistor body comprising a monocrystalline semiconductor material;
a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
a source and a drain coupled to the transistor body on opposite sides of the gate stack;
a front-side interconnect metallization layer over a first side of the transistor body and the field isolation dielectric, the front-side interconnect metallization layer coupled to a first one of the source, drain, or gate electrode; and
a back-side interconnect metallization layer over a second side of the body and the field isolation dielectric, the back-side interconnect metallization layer coupled to a second one of the source, drain, or gate electrode, and wherein the front-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the back-side interconnect metallization layer, or the back-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the front-side interconnect metallization layer.
10. The IC structure of claim 9 , wherein the front-side interconnect metallization layer comprises one or more of Ru, Rh, Pd, Jr, Pt, Au, W, Cr, or Co, and the back-side interconnect metallization layer comprises Cu.
11. The IC structure of claim 10 , wherein the back-side interconnect layer is coupled to the source, the front-side interconnect layer is coupled to the gate electrode, and the back-side interconnect metallization layer comprises features having at least one of larger lateral dimensions or greater thickness than the front-side interconnect metallization layer.