System for converting neuron current into neuron current-based time pulses in an analog neural memory in a deep learning artificial neural network
Numerous embodiments are disclosed for converting neuron current output by a vector-by-matrix multiplication (VMM) array into neuron current-based time pulses and providing such pulses as an input to another VMM array within an artificial neural network. Numerous embodiments are disclosed for converting the neuron current-based time pulses into analog current or voltage values if an analog input is needed for the VMM array.
1. A vector-by-matrix multiplication system, comprising:
an array of non-volatile memory cells arranged into rows and columns;
an input block coupled to the array to receive one or more input pulses, convert the one or more input pulses into an analog voltage, and apply the analog voltage to a word line or a control gate line in the array during a vector matrix multiplier operation; and
an output block coupled to the array to generate a set of digital bits in response to a neuron current drawn by the array during the vector matrix multiplier operation,
wherein the output block comprises:
a first operational amplifier comprising an inverting input terminal, a non-inverting input terminal, and an output terminal;
a reference current source to generate a reference current at an output thereof;
a first switch to selectively couple the output of the reference current source to the inverting input terminal of the first operational amplifier;
a second switch to selectively couple the neuron current to the inverting input terminal of the first operational amplifier;
a capacitor coupled between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier;
a third switch to selectively couple the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; and
a second operational amplifier comprising a non-inverting input terminal coupled to the output terminal of the first operational amplifier, an inverting input terminal, and an output terminal to generate a digital pulse in response to the neuron current.
2. The vector-by-matrix multiplication system of claim 1 , further comprising a gate arranged to receive the generated digital pulse and a clock to generate a series of pulses.
3. The vector-by-matrix multiplication system of claim 2 , further comprising a counter to count the series of pulses output by the gate to generate a count value comprising the digital bits.
4. A vector-by-matrix multiplication system, comprising:
an array of non-volatile memory cells arranged into rows and columns;
an input block coupled to the array to receive one or more input pulses, convert the one or more input pulses into an analog voltage, and apply the analog voltage to a word line or a control gate line in the array during a vector matrix multiplier operation; and
an output block coupled to the array to generate a set of digital bits in response to a neuron current drawn by the array during the vector matrix multiplier operation,
wherein the output block comprises:
an operational amplifier comprising an inverting input terminal, a non-inverting input terminal, and an output terminal;
a reference current source to draw a reference current from a node coupled to the non-inverting input terminal of the operational amplifier;
a capacitor coupled between the non-inverting input terminal of the operational amplifier and ground;
a switch to selectively couple the non-inverting input terminal of the operational amplifier to a bias voltage source; and
a logic circuit coupled to the output terminal of the operational amplifier;
wherein the neuron current is provided to the non-inverting input of the operational amplifier, and the set of digital bits are provided by the logic circuit.
5. The vector-by-matrix multiplication system of claim 4 , wherein the one or more input pulses comprises a single pulse.
6. The vector-by-matrix multiplication system of claim 4 , wherein the one or more input pulses comprises a series of pulses.
7. The vector-by-matrix multiplication system of claim 4 , wherein the input block comprises a digital-to-analog converter.
8. The vector-by-matrix multiplication system of claim 7 , wherein the digital-to-analog converter comprises a pulse-to-voltage converter.
9. The vector-by-matrix multiplication system of claim 4 , wherein the non-volatile memory cells in the array of non-volatile memory cells are split-gate flash memory cells.
10. The vector-by-matrix multiplication system of claim 4 , wherein the non-volatile memory cells in the array of non-volatile memory cells are stacked-gate flash memory cells.
11. A vector-by-matrix multiplication system, comprising:
an array of non-volatile memory cells arranged into rows and columns;
an input block coupled to the array to receive a first set of digital bits, convert the first set of digital bits into an analog voltage, and apply the analog voltage to a word line or a control gate line in the array during a vector matrix multiplier operation; and
an output block coupled to the array to generate a second set of digital bits in response to a neuron current drawn by the array during the vector matrix multiplier operation, wherein the output block comprises an integrating analog-to-digital converter to generate an output pulse in response to the neuron current and logic to convert the output pulse into a pulse series and count pulses in the pulse series to generate the second set of digital bits.
12. The vector-by-matrix multiplication system of claim 11 , wherein the input block comprises: a digital-to-analog converter.
13. The vector-by-matrix multiplication system of claim 12 , wherein the digital-to-analog converter comprises a digital data to voltage converter.
14. The vector-by-matrix multiplication system of claim 11 , wherein the non-volatile memory cells in the array of non-volatile memory cells are split-gate flash memory cells.
15. The vector-by-matrix multiplication system of claim 11 , wherein the non-volatile memory cells in the array of non-volatile memory cells are stacked-gate flash memory cells.
16. A vector-by-matrix multiplication system, comprising:
an array of non-volatile memory cells arranged into rows and columns;
an input block coupled to the array to receive a first set of digital bits, convert the first set of digital bits into an analog voltage and apply the analog voltage to a word line or a control gate line in the array during a vector matrix multiplier operation; and
an output block coupled to the array to generate a second set of digital bits as an output in response to a neuron current drawn by the array during the vector matrix multiplier operation,
wherein the output block comprises a circuit to map one or more digital pulses to the second set of digital bits using a mapping function or mapping table.
17. The vector-by-matrix multiplication system of claim 16 , wherein the mapping function or the mapping table simulates a sigmoid function.
18. The vector-by-matrix multiplication system of claim 16 , wherein the mapping function or the mapping table simulates a tanh function.
19. The vector-by-matrix multiplication system of claim 16 , wherein the mapping function or the mapping table simulates a ReLu function.
20. The vector-by-matrix multiplication system of claim 16 , wherein the mapping function or the mapping table simulates an activation function.
21. The vector-by-matrix multiplication system of claim 16 , wherein the mapping function or the mapping table quantizes the digital pulses.
22. The vector-by-matrix multiplication system of claim 16 , wherein the non-volatile memory cells in the array of non-volatile memory cells are split-gate flash memory cell.
23. The vector-by-matrix multiplication system of claim 16 , wherein the non-volatile memory cells in the array of non-volatile memory cells are stacked-gate flash memory cell.
24. A vector-by-matrix multiplication system, comprising:
an array of non-volatile memory cells arranged into rows and columns;
an input block coupled to the array to receive an input comprising one or more input pulses and to apply the input to an input line in the array during a vector matrix multiplier operation, wherein the one or more input pulses comprises a series of pulses, wherein a number of the input pulses in the series of pulses is proportional to a neuron current; and
an output block coupled to an output line from the array to generate a set of digital bits in response to an output on the output line during the vector matrix multiplier operation.
25. The vector-by-matrix multiplication system of claim 24 , wherein the output is a current.
26. The vector-by-matrix multiplication system of claim 24 , wherein the output is a voltage.
27. The vector-by-matrix multiplication system of claim 24 , wherein the output line is a bit line coupled to bit line terminals of a plurality of non-volatile memory cells in the array.
28. The vector-by-matrix multiplication system of claim 24 , wherein the output line is a source line coupled to source line terminals of a plurality of non-volatile memory cells in the array.
29. The vector-by-matrix multiplication system of claim 24 , wherein the output line is a word line coupled to word line terminals of a plurality of non-volatile memory cells in the array.
30. The vector-by-matrix multiplication system of claim 24 , wherein the output line is a control gate line coupled to control gate terminals of a plurality of non-volatile memory cells in the array.
31. The vector-by-matrix multiplication system of claim 24 , wherein the non-volatile memory cells in the array of non-volatile memory cells are split-gate flash memory cells.
32. The vector-by-matrix multiplication system of claim 24 , wherein the non-volatile memory cells in the array of non-volatile memory cells are stacked-gate flash memory cells.
33. A vector-by-matrix multiplication system, comprising:
an array of non-volatile memory cells arranged into rows and columns;
an input block coupled to the array to receive an input comprising one or more input pulses and apply the input to an input line in the array during a vector matrix multiplier operation, wherein the one or more input pulses comprises a series of pulses, wherein a number of the input pulses in the series of pulses is proportional to a neuron current; and
an output block coupled to an output line from the array.
34. The vector-by-matrix multiplication system of claim 33 , wherein the output block generates a set of digital bits in response to an output on the output line during the vector matrix multiplier operation.
35. The vector-by-matrix multiplication system of claim 33 , wherein the output line outputs a current signal.
36. The vector-by-matrix multiplication system of claim 33 , wherein the output line outputs a voltage signal.
37. The vector-by-matrix multiplication system of claim 33 , wherein the output line is a bit line coupled to bit line terminals of a plurality of non-volatile memory cells in the array.
38. The vector-by-matrix multiplication system of claim 33 , wherein the output line is a source line coupled to source line terminals of a plurality of non-volatile memory cells in the array.
39. The vector-by-matrix multiplication system of claim 33 , wherein the output line is a word line coupled to word line terminals of a plurality of non-volatile memory cells in the array.
40. The vector-by-matrix multiplication system of claim 33 , wherein the output line is a control gate line coupled to control gate terminals of a plurality of non-volatile memory cells in the array.
41. The vector-by-matrix multiplication system of claim 33 , wherein the non-volatile memory cells in the array of non-volatile memory cells are split-gate flash memory cells.
42. The vector-by-matrix multiplication system of claim 33 , wherein the non-volatile memory cells in the array of non-volatile memory cells are stacked-gate flash memory cells.
43. A vector-by-matrix multiplication system, comprising:
an array of non-volatile memory cells arranged into rows and columns;
an input block coupled to the array to receive an input comprising digital input bits and apply the input to an input line in the array during a vector matrix multiplier operation, wherein the input comprises a series of pulses, wherein a number of pulses in the series of pulses is proportional to a neuron current; and
an output block coupled to an output line from the array to generate one or more pulses during the vector matrix multiplier operation.
44. The vector-by-matrix multiplication system of claim 43 , wherein the output line outputs a current signal.
45. The vector-by-matrix multiplication system of claim 43 , wherein the output line outputs a voltage signal.
46. The vector-by-matrix multiplication system of claim 43 , wherein the output line is a bit line coupled to bit line terminals of a plurality of non-volatile memory cells in the array.
47. The vector-by-matrix multiplication system of claim 43 , wherein the output line is a source line coupled to source line terminals of a plurality of non-volatile memory cells in the array.
48. The vector-by-matrix multiplication system of claim 43 , wherein the output line is a word line coupled to word line terminals of a plurality of non-volatile memory cells in the array.
49. The vector-by-matrix multiplication system of claim 43 , wherein the output line is a control gate line coupled to control gate terminals of a plurality of non-volatile memory cells in the array.
50. The vector-by-matrix multiplication system of claim 43 , wherein the non-volatile memory cells in the array of non-volatile memory cells are split-gate flash memory cells.
51. The vector-by-matrix multiplication system of claim 43 , wherein the non-volatile memory cells in the array of non-volatile memory cells are stacked-gate flash memory cells.