Semiconductor device having chip stacked and molded
A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.
1. A semiconductor device, comprising:
an insulating layer;
a conductive member provided inside the insulating layer;
a chip disposed on a first surface of the insulating layer and connected to the conductive member;
a first barrier layer provided between the conductive member and the insulating layer; and
an electrode connected to the conductive member via the first barrier layer and having an interface contacting to the first barrier layer, a resistivity of the first barrier layer being higher than a resistivity of the conductive member, a portion of the electrode protruding from a second surface of the insulating layer, the interface being disposed between the first surface and the second surface, wherein
the conductive member includes:
a first via connected to the chip;
a second via connected to the electrode; and
an interconnect connected between the first via and the second via,
the second via and the interconnect are formed as one body;
the first barrier layer is disposed at least on a lower surface of the second via, on a side surface of the second via, and on a lower surface of the interconnect, and the second via is connected to the electrode via the first barrier layer.
2. The device according to claim 1 , further comprising a bump bonded to the electrode.
3. The device according to claim 2 , wherein the bump covers a side surface of the electrode and a lower surface of the electrode.
4. The device according to claim 1 , wherein the electrode includes nickel.
5. The device according to claim 1 , further comprising a second barrier layer provided between the first via and the interconnect.