IP Library Granted Patent US 11,455,397
Granted Patent B2
US 11,455,397 · App. 16/364,391 · Granted Sep 27, 2022

Secure boot assist for devices, and related systems, methods and devices

Inventors: Kerry Maletsky (Monument, CO); David Paul Arnold (Chandler, AZ); Nicolas Auguste Constant Schieli (Saint-Lambert, CA); Bryan Hunt (Colorado Springs, CO)
Assignee: Microchip Technology Incorporated
G06F21/575G06F21/34G06F21/572G06F9/4401G06F21/12G06F2221/2149
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Quick Facts
Patent No.
US 11,455,397
App. No.
16/364,391
Granted
Sep 27, 2022
Kind
B2
Abstract

Systems, methods, and devices of the disclosure relate, generally, to secure boot assist for devices. In one or more embodiments, a first device includes firmware that needs to be verified as secure as part of a secure boot process, and a second device assists the first device to secure the secure boot process. In some embodiments the second device verifies security of the firmware responsive to security data provided by the first device, or verifies security of a program provided by the first device, the program for verifying security of the firmware. In some embodiments the second device provides a program for verifying security of the firmware to the first device.

Claims (51)

1. A method, the method comprising:

disabling independent initiation of execution of code at a device to place the device in a restricted mode of operation;

while holding the device in the restricted mode of operation:

sending a program to the device via an interface enabled to control a central processing unit (CPU) of the device; and

initiating execution of the program at the device via the interface enabled to control the CPU; and

verifying security of firmware stored at the device responsive to the initiated execution of the program.

2. The method of claim 1 , wherein the sending the program to the device comprises sending a low level boot code to the device.

3. The method of claim 1 , wherein the disabling independent initiation of execution of code at the device is responsive to detecting that new firmware has been received at the device.

4. The method of claim 1 , wherein the verifying security of the firmware stored at the device responsive to the initiated execution of the program comprises:

performing a hashing function on operating code stored at a program memory of the device to obtain security data;

comparing the obtained security data to trusted security data; and

verifying the operating code is secure responsive to the comparing of the obtained security data to the trusted security data.

5. The method of claim 4 , further comprising verifying the operating code is secure responsive to detecting that the obtained security data matches the trusted security data.

6. The method of claim 4 , further comprising determining the operating code is unsecure responsive to detecting that the obtained security data does not match the trusted security data.

7. The method of claim 6 , further comprising holding the device in the restricted mode of operation until the program detects that secure operating code is installed at the device.

8. The method of claim 6 , further comprising restarting the device until the program detects that secure operating code is installed at the device.

9. The method of claim 1 , further comprising:

receiving a first verification result responsive to verifying that the firmware is secure; and

receiving a second verification result responsive to determining that the firmware is not secure.

10. The method of claim 9 , further comprising, responsive to receiving the first verification result:

instructing the device to execute the firmware upon exiting the restricted mode of operation; and

releasing the device from the restricted mode of operation.

11. The method of claim 9 , further comprising, responsive to receiving the second verification result:

holding the device in the restricted mode of operation until detecting that security of the firmware stored at the device is verified.

12. A secure boot-assisted system, comprising:

a first device comprising:

a memory having firmware stored thereon;

a processor; and

an interface for accessing and controlling the processor;

a second device operatively coupled to the first device, the second device comprising:

a persistent memory having stored thereon a program that, when executed by the processor of the first device, is configured to cause the processor to verify security of firmware stored at the program memory of the first device; and

a trusted sequence circuitry, comprising a logic circuit configured to use the interface to send the program to the first device and initiate execution of the program at the first device, and

wherein the logic circuit of the trusted sequence circuitry is configured to hold the first device in a restricted mode of operation while the processor verifies security of the stored firmware for the first device, and wherein the logic circuit of the trusted sequence circuitry is configured to control the interface of the first device to prevent at least some functionality of the first device.

13. The system of claim 12 , wherein the logic circuit of the trusted sequence circuitry is configured to assert a signal at a hardware input of the first device responsive to detecting that new firmware is stored at the first device.

14. The system of claim 13 , wherein the processor of the first device is configured to execute the program responsive to control signals provided by the interface.

15. The system of claim 12 , wherein the firmware comprises operating code, and wherein the program, when executed by the processor, is configured to cause the processor to:

hash the operating code stored in the memory of the first device to obtain a first digest;

compare the first digest to a second digest; and

verify the operating code is secure responsive to a comparison of the first digest and the second digest.

16. The system of claim 15 , wherein the program, when executed by the processor, is configured to cause the processor to:

determine the operating code is secure responsive to detecting that the first digest matches the second digest; and

determine the operating code is not secure responsive to detecting that the first digest does not match the second digest.

17. The system of claim 12 , wherein the logic circuit of the trusted sequence circuitry of the second device is configured, responsive to installing the program at the first device, to use the interface to instruct the first device to initiate execution of the program.

18. The system of claim 17 , wherein the program, when executed by the processor, is configured to cause the processor to:

provide a first verification result responsive to verifying that an operating code is secure; and

provide a second verification result responsive to determining that the operating code is not secure.

19. The system of claim 18 , wherein the firmware comprises operating code, and the logic circuit of the trusted sequence circuitry of the second device is configured, responsive to receiving the first verification result, to:

use the interface to instruct the first device to initiate execution of the operating code upon exiting the restricted mode of operation; and

release the first device from the restricted mode of operation.

20. The system of claim 18 , wherein the logic circuit of the trusted sequence circuitry of the second device is configured, responsive to receiving the second verification result, to hold the first device in the restricted mode of operation until detecting that secure firmware is installed at the first device.

21. The system of claim 12 , wherein the firmware comprises operating code for one or more of: an integrated embedded system, an operating system, an operating system loader, or individually installed applications.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2019
From: MALETSKY, KERRY; ARNOLD, DAVID PAUL; SCHIELI, NICOLAS AUGUSTE CONSTANT; HUNT, BRYAN
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 048778/0642 →
Continuity (2)
Provisional Application 62760636 · Nov 13, 2018
Related Publication 20200151336A1 · May 14, 2020