IP Library Granted Patent US 10,439,559
Granted Patent B2
US 10,439,559 · App. 16/371,255 · Granted Oct 8, 2019

Methods of adjusting gain error in instrumentation amplifiers

Inventors: Serban Motoroiu (Campina, RO); Jim Nolan (Chandler, AZ)
Assignee: Microchip Technology Incorporated
H03F1/12H03F1/342H03F3/45179H03F3/45183H03F3/45672H03G1/0023H03G1/0029H03G1/0088H03F2200/258H03F2200/261H03F2203/45048H03F2203/45138H03F2203/45341H03F2203/45342H03F2203/45466H03F2203/45494H03F2203/45504H03F2203/45511H03F2203/45521
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Quick Facts
Patent No.
US 10,439,559
App. No.
16/371,255
Granted
Oct 8, 2019
Kind
B2
Abstract

A current feed-back instrumentation amplifier (CFIA) comprises a differential pair with degeneration for amplifying small differential voltages in the presence of large common-mode voltages. The CFIA includes input and feedback transconductors and a trimming circuit that trims the back-bias voltages of the transistors in each transconductor. The trimming circuit includes a plurality of selectable resistors disposed in the signal path of the tail current in each transconductor. Each of the plurality of selectable resistors has a switch coupled to it. When a switch is closed, only the resistors up to the respective switch are in the signal path of the bulk-to-source voltage of the differentially paired transistors. The resistor trimming circuit reduces the mismatch between transconductances of the respective differential pair transistors, in turn reducing mismatch of the overall transconductances of the transconductors, and thereby reducing the CFIA's gain error.

Claims (76)

1. A method for gain error correction in a current-feedback instrumentation amplifier, said method comprising the steps of:

providing an input transconductor, the input transconductor comprising:

a first differential pair of transistors,

a first tail current source; and

a first trimming circuit coupled between the first tail current source and the first differential pair of transistors, and to a bulk of the first differential pair of transistors;

wherein the first trimming circuit varies a first back-bias voltage on the bulk of the first differential pair of transistors;

providing a feedback transconductor; and

adjusting the first trimming circuit to reduce a mismatch between the input transconductor and feedback transconductor.

2. The method according to claim 1 , further comprising the steps of providing first degeneration resistors coupled between the first differential pair of transistors and the first trimming circuit.

3. The method according to claim 1 , wherein the first trimming circuit comprises a plurality of series connected resistors and a plurality of switches coupled to the plurality of series connected resistors, whereby the first back-bias voltage is varied.

4. The method according to claim 1 , further comprising the steps of:

providing a modulator circuit between the first tail current source and a second tail current source, and the first trimming circuit and a second trimming circuit;

controlling the modulator circuit by alternating first and second phase states;

wherein:

during the first phase state the modulator circuit couples the first tail current source to the first trimming circuit and the second tail current source to the second trimming circuit; and

during the second phase state the modulator circuit couples the first tail current source to the second trimming circuit, and the second tail current source to the first trimming circuit.

5. A method for gain error correction in a current-feedback instrumentation amplifier, said method comprising the steps of:

providing an input transconductor;

providing a feedback transconductor, the feedback transconductor comprising:

a first differential pair of transistors;

a first tail current source; and

a first trimming circuit coupled between the first tail current source and the first differential pair of transistors, and to a bulk of the first differential pair of transistors;

wherein the first trimming circuit varies a first back-bias voltage on the bulk of the first differential pair of transistors; and

adjusting the first trimming circuit to reduce a mismatch between the input transconductor and feedback transconductor.

6. The method according to claim 5 , further comprising the steps of providing first degeneration resistors coupled between the first differential pair of transistors and the first trimming circuit.

7. The method according to claim 5 , wherein the first trimming circuit comprises a plurality of series connected resistors and a plurality of switches coupled to the plurality of series connected resistors, whereby the first back-bias voltage is varied.

8. The method according to claim 5 , further comprising the steps of:

providing a modulator circuit between the first tail current source and a second tail current source, and the first trimming circuit and a second trimming circuit;

controlling the modulator circuit by alternating first and second phase states;

wherein:

during the first phase state the modulator circuit couples the first tail current source to the first trimming circuit and the second tail current source to the second trimming circuit; and

during the second phase state the modulator circuit couples the first tail current source to the second trimming circuit, and the second tail current source to the first trimming circuit.

9. A current-feedback instrumentation amplifier having gain error correction, comprising:

a feedback transconductor;

an input transconductor comprising:

a first differential pair of transistors;

a first tail current source; and

a first trimming circuit coupled between the first tail current source and the first differential pair of transistors, and to a bulk of the first differential pair of transistors, the first trimming circuit configured to:

vary a first back-bias voltage on the bulk of the first differential pair of transistors; and

be adjusted to reduce a mismatch between the input transconductor and feedback transconductor.

10. The current-feedback instrumentation amplifier according to claim 9 , further comprising first degeneration resistors coupled between the first differential pair of transistors and the first trimming circuit.

11. The current-feedback instrumentation amplifier according to claim 9 , wherein the first trimming circuit comprises series connected resistors and a switch coupled to the series connected resistors, wherein the resistors and switch are configured to vary the first back-bias voltage.

12. The current-feedback instrumentation amplifier according to claim 9 , further comprising a modulator circuit coupled between the first tail current source and a second tail current source, and between the first trimming circuit and a second trimming circuit, wherein:

the modulator circuit is configured to alternate between first and second phase states;

during the first phase state the modulator circuit is configured to couple the first tail current source to the first trimming circuit and the second tail current source to the second trimming circuit; and

during the second phase state the modulator circuit is configured to couple the first tail current source to the second trimming circuit, and the second tail current source to the first trimming circuit.

13. The current-feedback instrumentation amplifier according to claim 12 , wherein the modulator circuit comprises:

a first switch coupled between the first tail current source and first degeneration resistors;

a second switch coupled between the first tail current source and second degeneration resistors;

a third switch coupled between the second tail current source and the first degeneration resistors; and

a fourth switch coupled between the second tail current source and the second degeneration resistors;

wherein:

the first and fourth switches are configured to close and the second and third switches are configured to open on a first phase state control signal; and

the second and third switches are configured to close and the first and fourth switches are configured to open on a second phase state control signal.

14. A current-feedback instrumentation amplifier having gain error correction, comprising:

an input transconductor; and

a feedback transconductor comprising:

a first differential pair of transistors;

a first tail current source; and

a first trimming circuit coupled between the first tail current source and the first differential pair of transistors, and to a bulk of the first differential pair of transistors, the first trimming circuit configured to:

vary a first back-bias voltage on the bulk of the first differential pair of transistors; and

be adjusted to reduce gain error between the input transconductor and feedback transconductor.

15. The current-feedback instrumentation amplifier according to claim 14 , further comprising first degeneration resistors coupled between the first differential pair of transistors and the first trimming circuit.

16. The current-feedback instrumentation amplifier according to claim 14 , wherein the first trimming circuit comprises series connected resistors and a switch coupled to the series connected resistors, wherein the resistors and switch are configured to vary the first back-bias voltage.

17. The current-feedback instrumentation amplifier according to claim 14 , further comprising a modulator circuit coupled between the first tail current source and a second tail current source, and between the first trimming circuit and a second trimming circuit, wherein:

the modulator circuit is configured to alternate between first and second phase states;

during the first phase state the modulator circuit is configured to couple the first tail current source to the first trimming circuit and the second tail current source to the second trimming circuit; and

during the second phase state the modulator circuit is configured to couple the first tail current source to the second trimming circuit, and the second tail current source to the first trimming circuit.

18. The current-feedback instrumentation amplifier according to claim 17 , wherein the modulator circuit comprises:

a first switch coupled between the first tail current source and first degeneration resistors;

a second switch coupled between the first tail current source and second degeneration resistors;

a third switch coupled between the second tail current source and the first degeneration resistors; and

a fourth switch coupled between the second tail current source and the second degeneration resistors;

wherein:

the first and fourth switches are configured to close and the second and third switches are configured to open on a first phase state control signal; and

the second and third switches are configured to close and the first and fourth switches are configured to open on a second phase state control signal.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2019
From: MOTOROIU, SERBAN; NOLAN, JIM
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 048752/0402 →