Array of three-gate flash memory cells with individual memory cell read, program and erase
View Patent ↗A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.
1. A memory device, comprising:
a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region,
a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and
a program-erase gate disposed over and insulated from the source region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the rows of memory cells includes a select gate line that electrically connects together all the select gates of the memory cells for the row of memory cells; and
each of the columns of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the column of memory cells.
2. The memory device of claim 1 , wherein for each of the memory cells, the floating gate extends over and is insulated from a portion of the source region.
3. The memory device of claim 1 , wherein for each of the memory cells, the select gate has a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.
4. The memory device of claim 1 , wherein for each of the memory cells, the program-erase gate has a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.
5. The memory device of claim 1 , wherein:
the memory cells are arranged in pairs of the memory cells; and
each of the pairs of memory cells shares one of the source regions and one of the source lines.