Charge-based digital to analog converter with second order dynamic weighted algorithm
A method includes receiving samples of digital to analog converter (DAC), partitioning the samples to unit-DACs based upon previous partitions of inputs to the unit-DACs to cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs, including partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm. The algorithm includes, for each DAC input, determining a first partition of the DAC input that would cancel an (n−1)th order previously integrated non-linearity, adding an equivalent DAC input of the first partition to the DAC input to obtain a total DAC input, using a first order application of the total DAC input to the inputs of the unit-DACs to yield a second partition of DAC input, summing the first and second partitions generate a final partition, and, based on the final partition, computing non-linearity remainders at each order of integration.
1. A digital to analog converter (DAC), comprising:
a summing circuit;
at least two unit-DACs connected in parallel, wherein:
each unit-DAC:
includes a unit-DAC input;
is configured to output an analog value proportional to its unit-DAC input in an inherently linear manner synchronous with a clock signal;
includes a gain mismatch when compared to other unit-DACs of the DAC;
the summing circuit is configured to sum outputs of the unit-DACs and output the sum as output of the DAC; and
a calculation engine configured to:
receive a plurality of successive samples of DAC input sampled according to the clock signal;
for each sample received, partition the sample of DAC input to the unit-DACs based upon previous partitions of inputs to the unit-DACs, so that a sum of the unit DAC inputs is equal to an input of the DAC;
using integration of a plurality of successive DAC outputs, cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs; and
partition samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm, wherein n is greater than one, for each DAC input, including configuring the calculation engine to:
determine a first partition of the DAC input that would cancel an (n−1)th order previously integrated non-linearity;
compute an equivalent DAC input of the first partition of DAC input;
add the equivalent DAC input to the DAC input to obtain a total DAC input;
use a first order algorithm to apply the total DAC input to the inputs of the unit-DACs to cancel out an nth order previously integrated non-linearity and yield a second partition of DAC input;
sum the first partition of DAC input and the second partition of DAC input to generate a final partition, the final partition to be used as inputs to the unit-DACs for a current sample of the DAC input; and
based on the final partition of DAC input, compute non-linearity remainders at each order of integration.
2. The DAC of claim 1 , wherein the calculation engine is further configured to cancel out non-linearity of the DAC by partitioning DAC input, in average over successive inputs, so that each unit-DAC input at each order of integration receives a same integrated value of input for each order of integration defined in the partitioning algorithm.
3. The DAC of claim 1 , wherein:
the analog values to be output by each unit-DAC include a charge to be transferred, proportional to its unit-DAC input; and
the output of the DAC is equal to a sum of charge transferred by the unit-DACs.
4. The DAC of claim 1 , wherein the calculation engine is further configured to:
during a partitioning algorithm to cancel out non-linearity of the DAC by integrating non-linearity to an nth order, determine a failure of results to converge;
upon determining the failure of results to converge, perform another partitioning algorithm to cancel out non-linearity of the DAC by integrating non-linearity to an order lower than the nth-order.
5. The DAC of claim 4 , wherein the calculation engine is further configured to, after performing the other algorithm to cancel out non-linearity of the DAC by integrating non-linearity to the order lower than the nth-order, reuse the algorithm to cancel out non-linearity of the DAC by integrating non-linearity to the nth order.
6. The DAC of claim 1 , wherein the calculation engine is further configured to
define an order of partitioning, wherein unit-DACs are assigned input from the DAC input with a priority according to the defined order.
7. The DAC of claim 6 , wherein the calculation engine is further configured to, between successive partitions of DAC input to the unit-DACs, shuffle the defined order, the shuffling configured to break periodicity of output of the DAC.
8. The DAC of claim 6 , wherein:
the calculation engine is further configured to access a memory for each order of integration to be used by partitioning algorithms;
each memory includes a two-dimensional array of memory locations;
each column of each two-dimensional array is configured to represent each unit-DAC; and
at each order of integration, each row of the two-dimensional array is configured to represent an integrated value of the unit-DAC inputs at the order of integration or a representation of the non-linearity remainder of each unit-DAC outputs integrated at the order of integration.
9. The DAC of claim 8 , wherein for a first order of integration of non-linearity, the two-dimensional array of memory locations may be configured to represent a given unit-DAC input with a single bit per column.
10. The DAC of claim 8 , wherein the calculation engine is further configured to:
determine that attempts to provide the same integrated value for each unit-DAC input for a given order of integration with a partitioning algorithm will not succeed and lead to a memory overflow;
based on the determination that the attempts will not succeed, resetting one or more rows of the two-dimensional array representing the given order of integration non-linearity remainders so that the memory overflow is removed.
11. The DAC of claim 10 , wherein the calculation engine is further configured to:
determine that attempts to provide the same integrated value for each unit-DAC input for a given order of integration will not succeed with an nth-order partitioning algorithm; and
perform an (n−1)th order partitioning algorithm to provide a cancellation of the non-linear remainders at the order (n−1).
12. The DAC of claim 8 , wherein:
a given input for the DAC is configured to be expressed in an input count, wherein individual elements of the input count represents a value to be converted by a given unit-DAC and element of the input count is assigned to a given unit-DAC; and
the calculation engine is configured to partition samples of DAC input to the unit-DACs to assign input to unit-DACs by:
successively filling, according to the defined order of partitioning, memory locations of one of the two-dimensional arrays with an element of the input count until all elements of the input count are assigned to memory locations;
wherein the filling made to the memory locations of the one of the two-dimensional arrays is summed by column to an empty one-dimensional array to obtain a partition of the DAC input to unit-DACs;
wherein the filling is configured to cancel non-linearity remainders in the two-dimensional arrays.
13. The DAC of claim 12 , wherein the calculation engine is configured to perform the filling in a one-by-one sequential order manner.
14. The DAC of claim 12 , wherein the calculation engine is configured to perform filling of subsequent orders of integration by summing remainders of non-linearity based upon partitioning and the current state of the two-dimensional arrays.
15. The DAC of claim 12 , wherein the calculation engine is further configured to:
determine a maximum input range for an individual unit-DAC for a given DAC input;
determine whether a column for the individual unit-DAC has been filed with elements of the input count for the given DAC input so as to reach the maximum input range; and
based on a determination that the column has reached the maximum input range for the given DAC input, omitting further filling of the column for the given DAC input.
16. The DAC of claim 12 , wherein the calculation engine is further configured to fill unfilled bottom rows of the two-dimensional arrays before filling other rows of the two-dimensional arrays.
17. The DAC of claim 12 , wherein the calculation engine is further configured to:
determine whether a given column of the two-dimensional arrays are filled to capacity during a given DAC input; and
based upon the determination that the given column is filled to capacity, omitting further filling of the column for the given DAC input.
18. The DAC of claim 12 , wherein the calculation engine is further configured to, upon attempting to fill a memory location in a given column of the two-dimensional arrays, determine whether the given column has been prevented from accepting further filling with elements.
19. The DAC of claim 12 , wherein the calculation engine is further configured to, after filling the memory locations of the two-dimensional arrays with a given DAC input, clearing completely filled rows of the two-dimensional arrays.
20. A method, comprising:
accessing at least two unit-DACs connected in parallel, wherein each unit-DAC:
includes a unit-DAC input;
is configured to output an analog value proportional to its unit-DAC input in an inherently linear manner synchronous with a clock signal; and
includes a gain mismatch when compared to other unit-DACs of the DAC;
summing outputs of the unit-DACs and output the sum as output of the DAC;
receiving a plurality of successive samples of DAC input sampled according to the clock signal;
for each sample received, partitioning the sample of DAC input to the unit-DACs based upon previous partitions of inputs to the unit-DACs, so that a sum of the unit DAC inputs is equal to an input of the DAC;
using integration of a plurality of successive DAC outputs, cancelling out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs; and
partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm, wherein n is greater than one, for each DAC input, including:
determining a first partition of the DAC input that would cancel an (n−1)th order previously integrated non-linearity;
computing an equivalent DAC input of the first partition of DAC input;
adding the equivalent DAC input to the DAC input to obtain a total DAC input;
using a first order algorithm to apply the total DAC input to the inputs of the unit-DACs to cancel out an nth order previously integrated non-linearity and yield a second partition of DAC input;
summing the first partition of DAC input and the second partition of DAC input to generate a final partition, the final partition to be used as inputs to the unit-DACs for a current sample of the DAC input; and
based on the final partition of DAC input, computing non-linearity remainders at each order of integration.