IP Library Granted Patent US 11,233,118
Granted Patent B2
US 11,233,118 · App. 16/400,475 · Granted Jan 25, 2022

Integrated circuit device having dielectric layer, and method and apparatus for manufacturing the integrated circuit device

Inventors: Young-Lim Park (Anyang-si, KR); Sun-Min Moon (Yongin-si, KR); Chang-Hwa Jung (Seoul, KR); Young-Geun Park (Suwon-si, KR); Jong-Bom Seo (Seoul, KR); Kyu-Ho Cho (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L28/75C23C16/45536
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Quick Facts
Patent No.
US 11,233,118
App. No.
16/400,475
Granted
Jan 25, 2022
Kind
B2
Abstract

An integrated circuit (IC) device includes an electrode, a dielectric layer facing the electrode, and a plurality of interface layers interposed between the electrode and the dielectric layer and including a first metal. The plurality of interface layers includes a first interface layer and a second interface layer. An oxygen content of the first interface layer is different from an oxygen content of the second interface layer.

Claims (60)

1. An integrated circuit device, comprising:

a substrate;

an electrode disposed on the substrate;

a dielectric layer disposed on the electrode,

wherein the electrode is disposed between the substrate and the dielectric layer; and

a plurality of interface layers interposed between the electrode and the dielectric layer and comprising a first metal,

wherein the plurality of interface layers comprises a first interface layer and a second interface layer disposed between the electrode and the dielectric layer, an oxygen content of the first interface layer is different from an oxygen content of the second interface layer, and each of the first interface layer and the second interface layer includes oxygen.

2. The integrated circuit device of claim 1 , wherein

each of the first interface layer and the second interface layer comprises an oxide of the first metal,

the first interface layer is disposed closer to the dielectric layer than the second interface layer, and

the oxygen content of the first interface layer is greater than the oxygen content of the second interface layer.

3. The integrated circuit device of claim 1 , wherein

the second interface layer is spaced apart from the dielectric layer,

the first interface layer is interposed between the second interface layer and the dielectric layer, and

the oxygen content of the second interface layer is less than the oxygen content of the first interface layer.

4. The integrated circuit device of claim 1 , wherein

the first interface layer is in contact with the dielectric layer and comprises an oxide of the first metal, and

the second interface layer is in contact with the electrode and comprises the first metal.

5. The integrated circuit device of claim 1 , wherein the electrode comprises the first metal, a nitride of the first metal, an oxide of the first metal, or a combination of the first metal, the nitride of the first metal, and the oxide of the first metal.

6. The integrated circuit device of claim 1 , wherein the electrode comprises a nitride of a second metal that is different from the first metal.

7. The integrated circuit device of claim 1 , wherein

the dielectric layer comprises a second metal that is different from the first metal, and

an electronegativity of the first metal is greater than an electronegativity of the second metal.

8. The integrated circuit device of claim 1 , wherein the first metal is selected from Mo, Nb, Sn, Ta, Ti, In, Ni, Co, W, and Ru.

9. The integrated circuit device of claim 1 , wherein the first interface layer and the second interface layer comprise different materials from each other and are selected from Mo, MoO 2 , and MoO 3 , respectively.

10. The integrated circuit device of claim 1 , wherein the first interface layer and the second interface layer comprise different materials from each other and are selected from Nb, NbO, NbO 2 , and Nb 2 O 5 , respectively.

11. An integrated circuit device, comprising:

a lower electrode and an upper electrode facing each other;

a dielectric layer interposed between the lower electrode and the upper electrode;

a lower interface layer interposed between the lower electrode and the dielectric layer and comprising a first metal; and

an upper interface layer interposed between the dielectric layer and the upper electrode and comprising the first metal,

wherein the lower interface layer comprises a first inner interface layer that is in contact with the dielectric layer and has a first oxygen content, and a first outer interface layer disposed between the first inner interface layer and the lower electrode and having a second oxygen content that is lower than the first oxygen content,

wherein the upper interface layer comprises a second inner interface layer that is in contact with the dielectric layer and has a third oxygen content, and a second outer interface layer disposed between the second inner interface layer and the upper electrode and having a fourth oxygen content that is lower than the third oxygen content,

wherein each of the first inner interface layer, the first outer interface layer, the second inner interface layer, and the second outer interface layer includes oxygen.

12. The integrated circuit device of claim 11 , wherein each of the first and second outer interface layers comprises a conductive layer.

13. The integrated circuit device of claim 11 , wherein

each of the first and second inner interface layers is in contact with the dielectric layer and comprises an oxide M x O y of the first metal, wherein M is the first metal, x is equal to 1 or 2, y is an integer, and 1≤y≤5, and

each of the first and second outer interface layers comprises an oxide M q O r of the first metal, wherein M is the first metal, q is equal to 1, and r is equal to 1 or 2.

14. The integrated circuit device of claim 11 , wherein

the dielectric layer comprises a second metal that is different from the first metal, and

an electronegativity of the first metal is greater than an electronegativity of the second metal.

15. The integrated circuit device of claim 11 , wherein at least one of the lower electrode and the upper electrode comprises the first metal, a nitride of the first metal, an oxide of the first metal, or a combination of the first metal, the nitride of the first metal, and the oxide of the first metal.

16. The integrated circuit device of claim 11 , wherein

each of the first and second inner interface layers comprises MoO 2 , MoO 3 , or a combination of MoO 2 and MoO 3 , and

each of the first and second outer interface layers comprises Mo, MoO 2 , or a combination of Mo and MoO 2 .

17. The integrated circuit device of claim 11 , wherein

each of the first and second inner interface layers comprises NbO, NbO 2 , Nb 2 O 5 , or a combination of NbO, NbO 2 and Nb 2 O 5 , and

each of the first and second outer interface layers comprises Nb, NbO, NbO 2 , or a combination of Nb, NbO and NbO 2 .

18. An integrated circuit device, comprising:

a lower electrode and an upper electrode facing each other;

a dielectric layer interposed between the lower electrode and the upper electrode;

a lower interface layer interposed between the lower electrode and the dielectric layer and comprising a first metal; and

an upper interface layer interposed between the dielectric layer and the upper electrode and comprising the first metal,

wherein the lower interface layer comprises a first inner interface layer that is in contact with the dielectric layer and has a first oxygen content, and a first outer interface layer disposed between the first inner interface layer and the lower electrode and having a second oxygen content that is lower than the first oxygen content,

wherein the upper interface layer comprises a second inner interface layer that is in contact with the dielectric layer and has a third oxygen content, and a second outer interface layer disposed between the second inner interface layer and the upper electrode and having a fourth oxygen content that is lower than the third oxygen content,

wherein at least one of the lower electrode and the upper electrode comprises the first metal, an oxide of the first metal, or a combination of the first metal and the oxide of the first metal,

wherein each of the first inner interface layer, the first outer interface layer, the second inner interface layer, and the second outer interface layer includes oxygen.

19. The integrated circuit device of claim 18 , wherein the first metal is selected from Mo, Nb, Sn, W, and Ru, and

at least one of the lower electrode and the upper electrode comprises a conductive layer including Mo, Nb, Sn, SnO, W, Ru, or a combination thereof.

20. The integrated circuit device of claim 18 , wherein the dielectric layer comprises a second metal that is different from the first metal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2019
From: PARK, YOUNG-LIM; MOON, SUN-MIN; JUNG, CHANG-HWA; PARK, YOUNG-GEUN; SEO, JONG-BOM; CHO, KYU-HO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 049051/0757 →
Priority Claims (1)
KR 10-2018-0057433 · May 18, 2018 · national
Continuity (1)
Related Publication 20190355804A1 · Nov 21, 2019
Cited By (2)
US 12,349,373 US 12,604,486