ReRAM memory cell having dual word line control
A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.
1. A method for programming a ReRAM memory cell that includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode at a bit line node and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device at its second electrode to a source line node, each of the two series-connected select transistors having a gate connected to a separate control line, the method comprising:
determining if the ReRAM cell is selected for programming;
if the ReRAM cell is selected for programming, biasing the bit line node at a first voltage potential, biasing the source line node at a second voltage potential less than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to program the ReRAM device in the ReRAM cell, and supplying the gate of the one of the series-connected transistors having its source connected to the source line node with positive voltage pulses having a first magnitude, and supplying the gate of the other one of the series-connected transistors with positive voltage pulses having a second magnitude higher than the first magnitude; and
if the ReRAM cell is unselected for programming, supplying the gate of the one of the series-connected transistors having its source connected to the source line node with a voltage potential insufficient to turn it on.
2. The method for programming according to claim 1 , further comprising:
if the ReRAM cell is unselected for programming, supplying the gate of the one of the series-connected transistors having its drain connected to the ReRAM device at its second electrode with a voltage potential such that the gate to drain voltage of the two series-connected select transistors is approximately equal.