Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same
An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers. The drain-select-level assemblies may be provided by forming drain-select-level openings through a drain-select-level sacrificial material layer, and by forming a combination of a cylindrical electrode portion and a first gate dielectric mayin each first drain-select-level opening while forming a second gate dielectric directly on a sidewall of each second drain-select-level opening in a second subset of the drain-select-level openings. A strip electrode portion is formed by replacing the drain-select-level sacrificial material layer with a conductive material. Structures filling the second subset of the drain-select-level openings may be used as dummy structures at a periphery of an array. The dummy structures are free of gate electrodes and thus prevents a leakage current therethrough.
1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory stack structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced apart along a second horizontal direction, wherein each of the memory stack structures comprises a memory film and a memory-level channel portion contacting an inner sidewall of the memory film;
an array of drain-select-level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures along the first horizontal direction and the second horizontal direction, wherein each of the drain-select-level assemblies comprises a drain-select-level channel portion contacting a respective memory-level channel portion and a drain region contacting an upper end of the drain-select-level channel portion;
a strip electrode portion laterally surrounding respective rows of drain-select-level assemblies; and
a drain-select-level isolation strip comprising at least one dielectric material and contacting the strip electrode portion and sidewalls of a row of drain-select-level assemblies;
wherein the drain-select-level assemblies comprise:
first drain-select-level assemblies including a respective first drain region that is contacted by a respective drain contact via structure; and
second drain-select-level assemblies including a respective second drain region, wherein an entirety of top surfaces of the second drain regions contacts a dielectric bottom surface of a contact level dielectric layer;
wherein each of the drain-select-level channel portions extends through, and contacts a sidewall of, an insulating spacer layer that overlies the array of memory stack structures;
wherein each of the first drain-select-level assemblies comprises a respective first gate dielectric that vertically extends straight from a horizontal plane including top surface of the drain-select-level assemblies to a top surface of the insulating spacer layer; and
wherein each of the second drain-select-level assemblies comprises a respective second gate dielectric having a greater lateral extent at a lower bulging portion thereof than at an upper portion thereof.
2. The three-dimensional memory device of claim 1 , wherein the array of memory stack structures and the array of drain-select-level assemblies are located in a memory array region in which each layer within the alternating stack is present.
3. The three-dimensional memory device of claim 2 , wherein:
the alternating stack comprises a staircase region in which the electrically conductive layers have variable lateral extents that decrease with a vertical distance from the substrate;
the second drain-select-level assemblies are located at a periphery of the memory array region adjacent to the staircase region; and
the first drain-select-level assemblies are laterally spaced apart from the staircase region by a greater lateral distance than the second drain-select-level assemblies are from the staircase region.