IP Library Granted Patent US 10,643,568
Granted Patent B2
US 10,643,568 · App. 16/408,593 · Granted May 5, 2020

Multi-mode low current dual voltage self-regulated LCD pump system

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Quick Facts
Patent No.
US 10,643,568
App. No.
16/408,593
Granted
May 5, 2020
Kind
B2
Abstract

A bias voltage generator circuit may include a mode control circuit, a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals, and a charge pump circuit configured to receive the clock signals. The charge pump circuit may be coupled with the mode control circuit and operable to output selectable output voltages according to input from the mode control circuit. The output selectable voltages may depend upon the clock signals.

Claims (54)

1. A bias voltage generator circuit comprising:

a mode control circuit;

a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals; and

a charge pump circuit configured to receive the clock signals, coupled with the mode control circuit, and further configured to output selectable output voltages according to input from the mode control circuit, the output selectable voltages to depend upon the clock signals, the clock signals to include non-overlapping pulses of a base signal and one or more phased signals.

2. The bias voltage generator circuit according to claim 1 , wherein the phased signals are to be selected according to specified output of the charge pump circuit.

3. The bias voltage generator circuit according to claim 1 , wherein the charge pump circuit is configured to output bias voltages based upon the presence of alternating ones of the phased signals.

4. The bias voltage generator circuit according to claim 1 , wherein the charge pump circuit is configured to output a voltage based on a number of different phased signals.

5. The bias voltage generator circuit according to claim 1 , wherein the charge pump circuit is configured to output a bias voltage with a current, the current based upon a number of different phased signals.

6. The bias voltage generator circuit according to claim 1 , wherein the mode control circuit is configured to select between a plurality of operating modes to define output of the charge pump circuit.

7. The bias voltage generator circuit according to claim 6 , wherein a first operating mode is configured to provide for a bias voltage with a first current for an LCD and a second operating mode is configured to provide the bias voltage with a second current for the LCD.

8. A microcontroller comprising:

a bias voltage generator circuit; and

an output routing circuit, the output routing circuit configured to route output from the bias voltage generator circuit to a display;

wherein the bias voltage generator circuit comprises:

a mode control circuit;

a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals; and

a charge pump circuit configured to receive the clock signals, coupled with the mode control circuit, and operable to output selectable output voltages according to input from the mode control circuit, the output selectable voltages to depend upon the clock signals, the clock signals to include non-overlapping pulses of a base signal and one or more phased signals.

9. The microcontroller according to claim 8 , wherein the phased signals are to be selected according to specified output of the charge pump circuit.

10. The microcontroller according to claim 8 , wherein the charge pump circuit is configured to output bias voltages based upon the presence of alternating ones of the phased signals.

11. The microcontroller according to claim 8 , wherein the charge pump circuit is configured to output a voltage based on a number of different phased signals.

12. The microcontroller according to claim 8 , wherein the charge pump circuit is configured to output a bias voltage with a current, the current based upon a number of different phased signals.

13. The microcontroller according to claim 8 , wherein the mode control circuit is configured to select between a plurality of operating modes to define output of the charge pump circuit.

14. The microcontroller according to claim 13 , wherein a first operating mode is configured to provide for a bias voltage with a first current for an LCD and a second operating mode is configured to provide the bias voltage with a second current for the LCD.

15. A method, comprising:

generating a plurality of clock signals; and

outputting selectable output voltages according to input from a mode control circuit, the output selectable voltages to depend upon the clock signals, the clock signals including non-overlapping pulses of a base signal and one or more phased signals.

16. The method according to claim 15 , wherein the phased signals are selected according to specified output of the charge pump circuit.

17. The method according to claim 16 , wherein:

in a first operating mode, providing a bias voltage with a first current for an LCD; and

in a second operating mode, providing the bias voltage with a second current for the LCD.

18. The method according to claim 15 , further comprising outputting bias voltages based upon the presence of alternating ones of the phased signals.

19. The method according to claim 15 , further comprising outputting a voltage based on a number of different phased signals.

20. The method according to claim 15 , further comprising outputting a bias voltage with a current, the current based upon a number of different phased signals.

21. The method according to claim 15 , further comprising selecting between a plurality of operating modes defining output of the output voltages.

22. A method, comprising:

providing a mode control circuit;

with a clock generator circuit coupled with the mode control unit, generating a plurality of clock signals;

with a charge pump circuit coupled with the mode control circuit:

receiving the clock signals; and

outputting selectable output voltages according to input from the mode control circuit, wherein the output selectable voltages depend upon the clock signals; and

providing a bootstrap circuit coupled between the clock generator circuit and the charge pump circuit.

23. A method, comprising:

generating a plurality of clock signals;

outputting selectable output voltages according to input from a mode control circuit, the output selectable voltages to depend upon the clock signals, the clock signals including non-overlapping pulses of a base signal and one or more phased signals;

in a first operating mode, providing a bias voltage for a 3V LCD; and

in a second operating mode, providing a bias voltage for a 5V LCD.

24. A method, comprising:

generating a plurality of clock signals;

outputting selectable output voltages according to input from a mode control circuit, the output selectable voltages to depend upon the clock signals, the clock signals including non-overlapping pulses of a base signal and one or more phased signals;

outputting a first voltage based upon the presence of a first number of different phased signals; and

outputting a second voltage based upon the presence of a second number of different phased signals;

wherein:

the second voltage is higher than the first voltage; and

the second number of different phased signals is greater than the first number of different phased signals.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2019
From: NAGEY, PETER K.; GUPTA, MUDIT; ZHOU, HUAMIN
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 049137/0904 →