Memory controllers, memory systems, solid state drives and methods for processing a number of commands
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.
1. A method of processing a number of commands, comprising:
receiving a number of task files each including at least one command from a host in an order;
performing, using hardware circuitry couplable to the host, an integrity check on the at least one command to verify at least one of a logical block address range or a valid command tag associated with the at least one command; and
processing the at least one command associated with a payload involving more than one of a plurality of back end channels of a memory controller.
2. The method of claim 1 , including distributing the payload associated with the at least one command amongst more than one of the plurality of back end channels, wherein the at least one command is a write command.
3. The method of claim 1 , including assembling the payload associated with the at least one command from more than one of the plurality of back end channels, wherein the at least one command is a read command.
4. The method of claim 1 , including:
determining an associated logical block address and sector count for each portion of the payload involving a respective one of the plurality of back end channels associated with the at least one command; and
modifying the at least one command distributed to the respective back end channel with the determined logical block address and sector count particular to the respective back end channel.
5. The method of claim 1 , including:
receiving the payload involving the more than one of the number of commands from the back end channels; and
communicating to the host the received payload in accordance with an order that is different from the order in which the number of commands were communicated by the host.
6. The method of claim 1 , including communicating to the host, a portion of the payload received from one of the back end channels without waiting to receive another portion of the payload from another one of the backend channels.
7. The method of claim 6 , including communicating to the host the portion of the payload received from the one of the back end channels without re-assembling the payload.
8. The method of claim 1 , including communicating an indicator of a completion status of a particular command of the number of commands, to the host, at completion of the particular command and independent of the order in which the commands were communicated by the host.
9. The method of claim 8 , including:
receiving a first command before receiving the particular command;
distributing the first command to a first back end channel;
distributing the particular command to a second back end channel; and
communicating the indicator of the completion status of the particular command to the host upon completion of the particular command and regardless of completion of the first command.
10. The method of claim 1 , including processing the number of commands to improve front end throughput before distributing the number of commands among the plurality of back end channels, the command processing including one or more of:
re-ordering the commands;
combining multiple commands; and
deleting commands.
11. The method of claim 10 , including distributing the payload associated with at least one combined command amongst more than one of the plurality of back end channels, wherein commands being combined have at least a portion of their payload involved with a particular one of the plurality of back end channels.
12. An apparatus, comprising:
a plurality of memory devices; and
a controller coupled to the plurality of memory devices and configured to:
receive a number of task files each including at least one command from a host in an order;
perform an integrity check on the at least one command to verify at least one of a logical block address range or a valid command tag associated with the at least one command; and
process the at least one command associated with a payload involving more than one of a plurality of back end channels of the memory controller.
13. The apparatus of claim 12 , wherein the controller is configured to process the number of commands to improve front end throughput before distributing the number of commands among the plurality of back end channels, the command processing including re-ordering the commands, combining multiple commands, deleting commands, or combinations thereof.
14. The apparatus of claim 12 , wherein the controller is configured to cause an indicator of a completion status of a particular command of the number of commands to be communicated to a host coupled to the controller upon completion of the particular command and independent of the order in which the commands were communicated by the host.
15. The apparatus of claim 14 , wherein the controller is configured to:
receive a first command before receiving the particular command;
distribute the first command to a first back end channel;
distribute the particular command to a second back end channel; and
communicate the indicator of the completion status of the particular command to the host upon completion of the particular command and regardless of completion of the first command.
16. The apparatus of claim 12 , wherein the controller is configured to:
determine an associated logical block address and sector count for each portion of the payload involving a respective one of the plurality of back end channels associated with the at least one command; and
modify the at least one command distributed to the respective back end channel with the determined logical block address and sector count particular to the respective back end channel.
17. A system, comprising:
a host;
a number of memory devices; and
a controller comprising:
a front end direct memory access module (DMA);
a command dispatcher coupled to the front end DMA; and
a plurality of back end channels communicatively coupled between a respective one of the number of memory devices and the front end DMA, wherein the controller is configured to:
receive a number of task files each including at least one command from the host in an order;
cause the command dispatcher to perform an integrity check on the at least one command to verify at least one of a logical block address range or a valid command tag associated with the at least one command; and
process the at least one command associated with a payload involving more than one of the number of back end channels.
18. The system of claim 17 , wherein the controller is configured to:
receive the payload involving the more than one of the number of commands from the back end channels; and
communicate to the host the received payload in accordance with an order that is different from the order in which the number of commands were communicated by the host.
19. The system of claim 17 , wherein the controller is configured to communicate to the host a portion of the payload received from one of the back end channels without waiting to receive another portion of the payload from another one of the backend channels.
20. The system of claim 19 , wherein the controller is configured to communicate to the host the portion of the payload received from the one of the back end channels without re-assembling the payload.
21. A method of processing a number of commands, comprising:
receiving a number of commands from a host in an order;
processing at least one command associated with a payload involving more than one of a plurality of back end channels of a memory controller;
determining an associated logical block address and sector count for each portion of the payload involving a respective one of the plurality of back end channels associated with the at least one command; and
modifying the at least one command distributed to the respective back end channel with the determined logical block address and sector count particular to the respective back end channel.
22. An apparatus, comprising:
a plurality of memory devices; and
a controller coupled to the plurality of memory devices and configured to:
receive a number of commands from a host in an order; and
process at least one command associated with a payload involving more than one of a plurality of back end channels of the memory controller;
determine an associated logical block address and sector count for each portion of the payload involving a respective one of the plurality of back end channels associated with the at least one command; and
modify the at least one command distributed to the respective back end channel with the determined logical block address and sector count particular to the respective back end channel.