Method and apparatus for data refresh for analog non-volatile memory in deep learning neural network
View Patent ↗Numerous embodiments of a data refresh method and apparatus for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Various embodiments of a data drift detector suitable for detecting data drift in flash memory cells within the VMM array are disclosed.
1. A method of detecting data drift in an array of non-volatile memory cells in an analog neuromorphic memory system, the method comprising:
selecting a sample of non-volatile memory cells within the array; and
detecting data drift in the selected cells for data drift, the detecting comprising:
programming each of the selected cells at one of N levels;
determining a difference between each pair of adjacent levels; and
comparing each difference against a target value.
2. The method of claim 1 , further comprising: when any difference exceeds the target value, performing a data restore.
3. The method of claim 2 , further comprising:
when any current of a restored cell does not meet a target, identifying the restored cell as a bad cell.
4. The method of claim 3 , further comprising:
replacing the bad cell with a redundant cell.
5. The method of claim 2 , wherein the data restore comprises cell tuning.
6. The method of claim 5 , wherein the cell tuning comprises iterative programming and verifying.
7. The method of claim 2 , wherein the data restore comprises cell tuning with a target amount corresponding to one of the N levels.
8. The method of claim 7 , wherein the target amount is stored in a look-up table.
9. The method of claim 2 , wherein the data restore comprises re-transferring training weights to the memory cells.
10. The method of claim 2 , wherein the memory cells are split gate memory cells.
11. The method of claim 2 , wherein the memory cells are stacked gate memory cells.
12. The method of claim 1 , further comprising: when any difference exceeds the target value, setting a data restore flag.
13. The method of claim 1 , wherein the memory cells are split gate memory cells.
14. The method of claim 1 , wherein the memory cells are stacked gate memory cells.