Method and apparatus for configuring array columns and rows for accessing flash memory cells
A non-volatile memory device is disclosed. The non-volatile memory device comprises an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells, and a row driver selectively coupled to a first row and a second row.
1. A non-volatile memory device comprising:
an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of adjacent rows of flash memory cells;
a row driver for asserting a first row and a second row at the same time during read operations to read data from a first cell in the first row and a second cell in the second row; and
a differential sense amplifier for outputting an output bit based on a difference between data read from the first cell and data read from the second cell, the differential sense amplifier comprising a built-in offset to cause the output bit to be a preferred value when the first cell and the second cell contain an identical value.
2. The non-volatile memory device of claim 1 , wherein the first row is in a first sector and the second row is in a second sector.
3. The non-volatile memory device of claim 1 , wherein the memory cells are split gate flash memory cells.
4. The non-volatile memory device of claim 2 , wherein program disturb of the first sector does not impact program disturb of the second sector.
5. The non-volatile memory device of claim 3 , further comprising an erase gate decoder selectively coupled to the array.
6. The non-volatile memory device of claim 3 , further comprising a control gate decoder selectively coupled to the array.
7. The non-volatile memory device of claim 3 , further comprising a source line decoder selectively coupled to the array.
8. The non-volatile memory device of claim 1 , wherein the memory cells are split gate flash memory cells.
9. The non-volatile memory device of claim 2 , wherein the memory cells are split gate flash memory cells.