Method of reducing injection type of program disturb during program pre-charge in memory device
Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.
1. An apparatus, comprising:
a set of memory cells arranged in NAND strings in a block, each NAND string comprising a channel extending from a source end to a drain end of the NAND string;
a respective bit line connected to the drain end of each NAND string;
a plurality of word lines connected to the set of memory cells and comprising a selected word line, drain-side word lines of the selected word line and source-side word lines of the selected word line, the source-side word lines are programmed, the drain side word lines are unprogrammed; and
a control circuit connected to the bit line and the word lines, the control circuit is configured to, in a program loop of a program operation:
perform a pre-charge phase in which a positive voltage is applied to the bit lines while a voltage applied to the selected word line and a voltage applied to the drain-side word lines allow the positive voltage to charge a region of the channel adjacent to the selected word line and the drain-side word lines, where the voltage applied to the selected word line is adjusted based on a risk factor for an injection type of program disturb on the selected word line; and
after the pre-charge phase, apply a program voltage to the selected word line.
2. The apparatus of claim 1 , wherein:
the voltage applied to the drain-side word lines is adjusted based on the risk factor.
3. The apparatus of claim 1 , wherein:
the voltage applied to the selected word line is relatively low when the risk factor indicates a risk of the injection type of program disturb is relatively high.
4. The apparatus of claim 1 , wherein:
the risk factor comprises a temperature provided by a temperature-sensing circuit;
the voltage applied to the selected word line is based on the temperature; and
the voltage applied to the selected word line is lower when the temperature is lower.
5. The apparatus of claim 1 , wherein:
the risk factor comprises a magnitude of the program voltage;
the voltage applied to the selected word line is based on the magnitude of the program voltage; and
the voltage applied to the selected word line is lower when the magnitude of the program voltage is higher.
6. The apparatus of claim 1 , wherein:
the risk factor comprises a distance between the source ends of the NAND strings and the selected word line;
the voltage applied to the selected word line is based on the distance; and
the voltage applied to the selected word line is lower when the distance is greater.
7. The apparatus of claim 6 , wherein:
the voltage applied to the drain-side word lines is based on the distance such that the voltage applied to the drain-side word lines is lower when the distance is greater; and
the voltage applied to the drain-side word lines is greater than the voltage applied to the selected word line.
8. The apparatus of claim 1 , wherein:
the plurality of word lines comprise an adjacent subset of source-side word lines of the selected word line; and
in the pre-charge phase, the control circuit is configured to apply a voltage to the adjacent subset of source-side word lines which is greater when the risk factor indicates a risk of the injection type of program disturb is greater.
9. The apparatus of claim 1 , wherein:
the plurality of word lines comprise source-side word lines of the selected word line;
in the pre-charge phase, the control circuit is configured to apply a voltage to a subset of the source-side word lines which is greater than a voltage applied to remaining word lines of the source-side word lines; and
the subset comprises multiple adjacent word lines and is adjacent to the selected word line.
10. The apparatus of claim 9 , wherein:
a number of word lines in the subset is chosen so that a probability of memory cells connected to the multiple adjacent word lines in one of the NAND strings are all in an erased state is below 0.5%.
11. The apparatus of claim 1 , wherein:
the plurality of word lines comprise source-side word lines of the selected word line;
in the pre-charge phase, the control circuit is configured to apply a voltage to a subset of the source-side word lines which is greater than a voltage applied to remaining word lines of the source-side word lines; and
the subset comprises multiple adjacent word lines and is non-adjacent to the selected word line.
12. The apparatus of claim 1 , wherein:
the NAND strings are arranged a plurality of sub-blocks in the block;
the program operation is for a selected sub-block of the plurality of sub-blocks;
the risk factor comprises a number of sub-blocks in the plurality of sub-blocks which are programmed before the selected sub-block;
the voltage applied to the selected word line is set based on the number of sub-blocks in the plurality of sub-blocks which are programmed before the selected sub-block; and
the voltage applied to the selected word line is lower when the number of sub-blocks in the plurality of sub-blocks which are programmed before the selected sub-block is higher.
13. A method, comprising:
performing a pre-charge phase of a program loop of a program operation for a set of memory cells, wherein the set of memory cells are arranged in NAND strings in a block, each NAND string comprising a channel extending from a source end to a drain end of the NAND string, a respective bit line is connected to the drain end of each NAND string, and a plurality of word lines are connected to the set of memory cells and comprise a selected word line, source-side word lines of the selected word line and drain-side word lines of the selected word line, the performing the pre-charge phase comprises:
applying a positive voltage to the bit lines to pre-charge a region of the channel adjacent to the drain-side word lines of the selected word line, and
during the applying of the positive voltage to the bit lines, applying a voltage to a subset of the source-side word lines which is greater than a voltage applied to remaining word lines of the source-side word lines, the voltage applied to the subset of the source-side word lines increases a floating voltage of a region of the channel adjacent to the subset of the source-side word lines to a level which is higher than a floating voltage of a region of the channel adjacent to the remaining word lines of the source-side word lines.
14. The method of claim 13 , wherein:
the subset comprises multiple adjacent word lines which are adjacent to the selected word line.
15. The method of claim 14 , wherein:
the voltage applied to the subset of the source-side word lines is set based on a number of word lines in the subset of the source-side word lines; and
the voltage applied to the subset of the source-side word lines is higher when the number of word lines in the subset of the source-side word lines is larger.
16. The method of claim 13 , wherein:
the subset comprises multiple adjacent word lines which are separated from the selected word line by multiple word lines.
17. An apparatus, comprising:
a set of memory cells arranged in NAND strings in a block, each NAND string comprising a source end and a drain end;
a respective bit line connected to the drain end of each NAND string;
a plurality of word lines connected to the set of memory cells and comprising a selected word line, source-side word lines of the selected word line and drain-side word lines of the selected word line, the drain-side word lines are unprogrammed and the source-side word lines are programmed; and
a control circuit configured to, in a program loop of a program operation,
perform a pre-charge phase in which a positive voltage is applied to the bit lines while a first voltage is applied to a first subset of adjacent word lines of the source-side word lines and a second voltage that is lower than the first voltage is applied to a second subset of adjacent word lines of the source-side word lines, wherein the first subset of adjacent word lines is adjacent to the second subset of adjacent word lines.
18. The apparatus of claim 17 , wherein:
the first subset of adjacent word lines is adjacent to the selected word line.
19. The apparatus of claim 18 , wherein:
the first voltage is set based on a number of word lines in the first subset of adjacent word lines; and
the first voltage is higher when the number of word lines in the first subset of adjacent word lines is larger.
20. The apparatus of claim 1 , wherein:
a region of the channel adjacent to the source-side word lines has a floating negative voltage while the positive voltage charges the region of the channel adjacent to the selected word line and the drain-side word lines.