IP Library Granted Patent US 10,566,439
Granted Patent B2
US 10,566,439 · App. 16/423,414 · Granted Feb 18, 2020

High power gallium nitride electronics using miscut substrates

Inventors: Isik C. Kizilyalli (San Francisco, CA); Dave P. Bour (Cupertino, CA); Thomas R. Prunty (Santa Clara, CA); Gangfeng Ye (Fremont, CA)
Assignee: NEXGEN POWER SYSTEMS, INC.
H01L29/66204H01L21/0243H01L21/0254H01L21/02389H01L21/02433H01L21/02458H01L21/02634H01L21/7605H01L29/045H01L29/0657H01L29/2003H01L29/6609H01L29/861H01L29/8613H01L29/0649
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Quick Facts
Patent No.
US 10,566,439
App. No.
16/423,414
Granted
Feb 18, 2020
Kind
B2
Abstract

A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.

Claims (27)

1. A field effect transistor comprising:

a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction towards the <1 1 00> direction by an angle ranging between −0.3° and −0.6° and towards the <11 2 0> direction by an angle ranging between −0.1° and −0.2°;

a first epitaxial layer coupled to the III-V substrate;

a second epitaxial layer coupled to the first epitaxial layer;

a drain contact in electrical contact with the III-V substrate;

a source contact in electrical contact with the first epitaxial layer; and

a gate contact in electrical contact with the second epitaxial layer.

2. The field effect transistor of claim 1 wherein the III-V substrate comprises an n-type GaN substrate.

3. The field effect transistor of claim 1 wherein the first epitaxial layer comprises an n-type GaN epitaxial layer and the second epitaxial layer comprises a p-type GaN epitaxial layer.

4. The field effect transistor of claim 1 further comprising an isolation region disposed laterally to the second epitaxial layer.

5. The field effect transistor of claim 1 further comprising a third epitaxial layer disposed between the second epitaxial layer and the gate contact, wherein a doping density of the third epitaxial layer is higher than a doping density of the second epitaxial layer.

6. The field effect transistor of claim 1 wherein the first epitaxial layer has a thickness greater than 5 μm.

7. The field effect transistor of claim 1 wherein a dopant concentration in the first epitaxial layer varies as a function of a thickness of the first epitaxial layer.

8. The field effect transistor of claim 1 wherein a dopant concentration in the second epitaxial layer varies as a function of a thickness of the second epitaxial layer.

9. A method of fabricating a field effect transistor, the method comprising:

providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction towards the <1 1 00> direction by an angle ranging between −0.3° and −0.6° and towards the <11 2 0> direction by an angle ranging between −0.1° and −0.2°;

growing a first epitaxial layer coupled to the III-V substrate;

growing a second epitaxial layer coupled to the first epitaxial layer;

forming a drain contact in electrical contact with the III-V substrate;

forming a source contact in electrical contact with the first epitaxial layer; and

forming a gate contact in electrical contact with the second epitaxial layer.

10. The method of claim 9 wherein the III-V substrate comprises an n-type GaN substrate.

11. The method of claim 9 wherein the first epitaxial layer comprises an n-type GaN epitaxial layer having a thickness greater than 3 μm and the second epitaxial layer comprises a p-type GaN epitaxial layer.

12. The method of claim 11 wherein the n-type GaN epitaxial layer has a thickness greater than 5 μm.

13. The method of claim 9 further comprising forming an isolation region disposed laterally to the second epitaxial layer.

14. The method of claim 9 further comprising forming a third epitaxial layer disposed between the second epitaxial layer and the gate contact, wherein a doping density of the third epitaxial layer is higher than a doping density of the second epitaxial layer.

15. The method of claim 9 wherein a dopant concentration in the first epitaxial layer or the second epitaxial layer varies as a function of thickness.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 66783 FRAME: 161. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 24, 2024
From: NEXGEN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 067217/0886 →
NUNC PRO TUNC ASSIGNMENT Recorded Apr 24, 2024
From: NEXGEN POWER SYSTEMS, INC.
To: NEXGEN (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 067852/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2024
From: NEXGEN POWER SYSTEMS, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 067172/0711 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2024
From: NEXGEN POWER SYSTEMS, INC.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 066783/0161 →
RELEASE OF SECURITY INTEREST Recorded Jul 26, 2021
From: SOUTH LAKE ONE LLC
To: NEXGEN POWER SYSTEMS, INC.
Reel/Frame 056973/0477 →
SECURITY INTEREST Recorded Oct 23, 2020
From: NEXGEN POWER SYSTEMS, INC.
To: SOUTH LAKE ONE LLC
Reel/Frame 054244/0822 →
Continuity (4)
Continuation 15697161 · Sep 6, 2017
Continuation 15156979 · May 17, 2016
Division 14071032 · Nov 4, 2013
Related Publication 20190348522A1 · Nov 14, 2019