IP Library › Granted Patent US 10,622,382

Granted Patent B2

US 10,622,382 · App. 16/430,484 · Granted Apr 14, 2020

Semiconductor device and display device

Inventors: Hajime Kimura (Kanagawa, JP); Atsushi Umezaki (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

H01L27/1225 G02F1/1339 G02F1/1368 G02F1/13306 G02F1/136213 G02F1/136286 G11C19/28 H01L27/088 H01L27/124 H01L27/127 H01L27/1244 H01L27/1251 H01L27/1255 H01L27/1288 H01L29/41733 H01L29/42384 H01L29/7869 H01L29/78696 G02F1/133345 G02F1/134309 G02F2001/133302 G02F2201/121 G02F2201/123 G09G3/3677 G09G2310/0251 G09G2310/08 G09G2330/021

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Quick Facts

Patent No.: US 10,622,382
App. No.: 16/430,484
Granted: Apr 14, 2020
Kind: B2

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Abstract

A semiconductor device including a circuit which does not easily deteriorate is provided. The semiconductor device includes a first transistor, a second transistor, a first switch, a second switch, and a third switch. A first terminal of the first transistor is connected to a first wiring. A second terminal of the first transistor is connected to a second wiring. A gate and a first terminal of the second transistor are connected to the first wiring. A second terminal of the second transistor is connected to a gate of the first transistor. The first switch is connected between the second wiring and a third wiring. The second switch is connected between the second wiring and the third wiring. The third switch is connected between the gate of the first transistor and the third wiring.

Claims (164)

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor;

a ninth transistor; and

a tenth transistor,

wherein the first transistor, the second transistor the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor have a same conductivity type,

wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fifth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the sixth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the eighth transistor,

wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the tenth transistor,

wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,

wherein the one of the source and the drain of the seventh transistor is electrically connected to a gate of the second transistor,

wherein the one of the source and the drain of the seventh transistor is electrically connected to a gate of the fourth transistor,

wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,

wherein the one of the source and the drain of the ninth transistor is electrically connected to a gate of the seventh transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the eighth transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the tenth transistor is electrically connected to the first wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a second wiring,

wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the second wiring,

wherein the other of the source and the drain of the seventh transistor is electrically connected to a third wiring,

wherein the other of the source and the drain of the ninth transistor is electrically connected to the third wiring,

wherein the other of the source and the drain of the ninth transistor is electrically connected to a gate of ninth transistor,

wherein a channel width of the third transistor is larger than a channel width of the sixth transistor,

wherein an L level of a signal input to the third wiring is approximately a first potential, and

wherein a potential of the first wiring is approximately the first potential.

2. The semiconductor device according to claim 1 , wherein the first transistor, the second transistor the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are n-channel transistors.

3. The semiconductor device according to claim 1 , wherein the first transistor, the second transistor the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor are p-channel transistors.

4. A semiconductor device comprising: