Heat dissipation structure including stacked chips surrounded by thermal interface material rings
The present disclosure describes heat dissipating structures that can be formed either in functional or non-functional areas of three-dimensional system on integrated chip structures. In some embodiments, the heat dissipating structures maintain an average operating temperature of memory dies or chips below about 90° C. For example, a structure includes a stack with chip layers, where each chip layer includes one or more chips and an edge portion. The structure further includes a thermal interface material disposed on the edge portion of each chip layer, a thermal interface material layer disposed over a top chip layer of the stack, and a heat sink over the thermal interface material layer.
1. A structure, comprising:
a stack of two or more chip layers, wherein a chip layer of the stack of two or more chip layers comprises:
a center portion comprising one or more chips; and
an edge portion surrounding the center portion and comprising:
a thermal interface material ring comprising a first material having a first thermal conductivity, and
a thermally conductive structure comprising a second material having a second thermal conductivity higher than the first thermal conductivity, wherein the thermally conductive structure extends vertically through the chip layer, and is in physical contact with the thermal interface material ring;
a thermal interface material layer disposed over a top chip layer of the stack; and
a heat sink over the thermal interface material layer.
2. The structure of claim 1 , wherein the thermally conductive structure is a first thermally conductive structure, and wherein the edge portion of the chip layer further comprises:
a dummy region located at the edge portion of the chip layer, wherein the dummy region comprises a dielectric material disposed on and in physical contact with the thermal interface material ring, wherein the dielectric material has a third thermal conductivity lower than the first thermal conductivity; and
a second thermally conductive structure laterally extending through the dielectric material of the dummy region, wherein the first thermally conductive structure, the second thermally conductive structure, and the thermal interface material ring are configured to channel heat generated in the stack through the edge portion of the chip layer towards the heat sink.
3. The structure of claim 2 , the first and second thermally conductive structures comprise a material with a thermal conductivity greater than about 200 W/m·K.
4. The structure of claim 1 , wherein the thermal interface material ring forms a continuous layer around the one or more chips of the chip layer.
5. The structure of claim 4 , wherein the continuous layer has a thickness between about 0.3 mm and about 0.8 mm.
6. The structure of claim 1 , wherein the one or more chips comprise memory chips.
7. A structure, comprising:
a plurality of chip layers, wherein a chip layer of the plurality of chip layers comprises:
one or more chips; and
an edge portion surrounding the one or more chips and comprising:
a thermal interface material (TIM) ring comprising a first material having a first thermal conductivity and surrounding the one or more chips, and
a thermally conductive structure comprising a second material having a second thermal conductivity higher than the first thermal conductivity, wherein the thermally conductive structure extends vertically through the chip layer, and is in physical contact with the thermal interface material ring; and
a TIM layer on the plurality of chip layers.
8. The structure of claim 7 , wherein the one or more chips comprise memory chips.
9. The structure of claim 7 , wherein the TIM ring forms a continuous layer around the one or more chips.
10. The structure of claim 9 , wherein the continuous layer has a thickness between about 0.3 mm and about 0.8 mm.
11. The structure of claim 7 , wherein the TIM ring is located in a non-functional area in the chip layer.
12. The structure of claim 7 , wherein the TIM layer comprises silver, aluminum nitride, silicon carbide, or combinations thereof.
13. The structure of claim 7 , wherein the TIM layer comprises a thermal grease with a thermal conductivity between about 1.5 W/(m·K) and about 15 W/(m·K).
14. The structure of claim 7 , wherein the TIM layer has a thickness between about 0.1 mm and about 0.5 mm.
15. The structure of claim 7 , wherein the thermally conductive structure, the TIM ring and the TIM layer are arranged to form a heat dissipation path from a bottom most chip layer of the plurality of chip layers to the TIM layer.
16. A structure, comprising:
a stack of two or more chip layers, wherein a chip layer of the stack of two or more chip layers comprises:
one or more chips; and
a non-functional region comprising:
a thermal interface material (TIM) ring comprising a first material having a first thermal conductivity; and
a thermally conductive structure comprising a second material having a second thermal conductivity higher than the first thermal conductivity, wherein the thermally conductive structure extends vertically through the chip layer, and is in physical contact with the thermal interface material ring;
a TIM layer on a top most chip layer in the stack of two or more chip layers; and
a heat sink on the TIM layer.
17. The structure of claim 16 , wherein the non-functional region further comprises a dielectric material.
18. The structure of claim 16 , wherein the TIM ring forms a continuous layer around the one or more chips.
19. The structure of claim 16 , wherein the TIM layer comprises silver, aluminum nitride, silicon carbide, or combinations thereof.
20. The structure of claim 16 , wherein the TIM layer comprises a thermal grease with a thermal conductivity between about 1.5 W/(m·K) and about 15 W/(m·K).