Forming a thin film resistor (TFR) in an integrated circuit device
A method is provided for forming a thin film resistor (TFR) in an integrated circuit (IC) including IC elements, e.g., memory components. A first contact etch stop layer is formed over the IC elements. A TFR layer stack including a TFR etch stop layer, a TFR film layer, and a second contact etch stop layer is formed over the first contact etch stop layer, and in some cases over one or more pre-metal dielectric layers. A patterned mask is formed over the IC stack, and the stack is etched, through both the first and second contact etch stop layers, to simultaneously form (a) first contact openings exposing contact regions of the IC elements and (b) second contact opening(s) exposing the TFR film layer. The first and second contact openings are filled with conductive material to form conductive contacts to the IC elements and the TFR film layer.
1. A method of forming an integrated circuit (IC) structure including a thin film resistor (TFR), the method comprising:
forming at least one IC memory element over a semiconductor substrate, the at least one IC memory element having at least one IC memory element contact region;
forming a first contact etch stop layer over the at least one IC memory element;
forming a TFR layer stack in a pre-metal dielectric region above the first contact etch stop layer and laterally offset from the at least one IC memory element contact region, wherein forming the TFR layer stack includes:
forming a TFR film layer, and
forming a second contact etch stop layer over the TFR film layer;
furnace annealing the TFR film layer to tune a temperature coefficient of resistance (TCR) value of the TFR film layer toward zero;
forming a patterned mask including at least one first mask opening aligned over the at least one IC memory element contact region and at least one second mask opening aligned over the TFR layer stack;
performing at least one etch through the first and second mask openings and through portions of the IC structure, including through both the first contact etch stop layer and the second contact etch stop layer, to simultaneously form (a) at least one first contact opening that exposes the at least one IC memory element contact region and (b) at least one second contact opening that exposes the TFR film layer; and
filling the at least one first contact opening and the at least one second contact opening with conductive material to form at least one conductive contact to the at least one IC memory element and at least one conductive contact to the TFR film layer.
2. The method of claim 1 , wherein:
forming the TFR layer stack in the pre-metal dielectric region comprises depositing a dielectric layer over the at least one IC memory element and over the first contact etch stop layer; and
the TFR layer stack is formed over the deposited dielectric layer.
3. The method of claim 1 , wherein:
forming the TFR layer stack in the pre-metal dielectric region comprises depositing multiple dielectric layers over the at least one IC memory element and over the first contact etch stop layer; and
the TFR layer stack is formed over the multiple dielectric layers.
4. The method of claim 1 , wherein forming the TFR layer stack in the pre-metal dielectric region comprises depositing at least one dielectric layer over the TFR layer stack.
5. The method of claim 1 , wherein the forming of the TFR layer stack is directly on the first contact etch stop layer.
6. The method of claim 1 , wherein the first contact etch stop layer and the second contact etch stop layer are formed from the same material.
7. The method of claim 1 , wherein the first contact etch stop layer and the second contact etch stop layer are each formed from SiN or other dielectric nitride.
8. The method of claim 1 , wherein the second contact etch stop layer has a greater thickness than the first contact etch stop layer.
9. The method of claim 1 , wherein the performing at least one etch to simultaneously form (a) at least one first contact opening that exposes the IC memory element contact region and (b) at least one second contact opening that exposes the TFR film layer comprises:
performing a first etch that exposes the first contact etch stop layer and the second contact etch stop layer; and
performing a second etch that extends through the first contact etch stop layer and second contact etch stop layer to expose the at least one IC memory element contact region and the TFR film layer.
10. The method of claim 1 , wherein the forming of the TFR layer stack further includes:
forming a TFR etch stop layer,
wherein forming the TFR film layer is over the formed TFR etch stop layer.
11. The method of claim 1 , comprising forming and annealing the TFR film layer prior to forming a first metal layer on the IC structure.
12. A method of forming a thin film resistor (TFR), the method comprising:
forming a memory element over a semiconductor substrate;
forming a first contact etch stop layer above the memory element;
forming a TFR film layer above the first contact etch stop layer;
furnace annealing the TFR film layer to tune a temperature coefficient of resistance (TCR) value of the TFR film layer toward zero;
forming a second contact etch stop layer over the TFR film layer, wherein the TFR film layer and the second contact etch stop layer are laterally offset from the contact pad;
forming a patterned mask having a first mask opening aligned over the memory element and at least one second mask opening aligned over the TFR film layer;
performing at least one etch through the first and second mask openings and through both the first contact etch stop layer and the second contact etch stop layer to form both (a) a first contact opening that exposes the memory element or a conductive contact region connected to the memory element and (b) at least one second contact opening that exposes the TFR film layer; and
filling the first contact opening and the at least one second contact opening with conductive material to form a first vertically-extending contact connected to the memory element or to the conductive contact region and at least one second vertically-extending contact connected to the TFR film layer.
13. The method of claim 12 , further comprising:
forming an IC memory element over the semiconductor substrate, wherein the conductive contact region provides a conductive coupling to the memory element; and
depositing at least one dielectric layer over the memory element, the memory element, and the first contact etch stop layer,
wherein the TFR film layer is formed over the at least one dielectric layer.
14. The method of claim 12 , further comprising forming a TFR layer stack directly on the first contact etch stop layer by:
forming a TFR etch stop layer directly on the first contact etch stop layer,
wherein said forming the TFR film layer is over the TFR etch stop layer.
15. The method of claim 12 , wherein the first contact etch stop layer and the second contact etch stop layer are formed from the same material.
16. The method of claim 12 , wherein the first contact etch stop layer and the second contact etch stop layer are each formed from SiN or other dielectric nitride.
17. The method of claim 12 , wherein the second contact etch stop layer has a greater thickness than the first contact etch stop layer.
18. The method of claim 12 , wherein the performing of at least one etch through the first and second mask openings and through both the first contact etch stop layer and the second contact etch stop layer to form both (a) a first contact opening that exposes the memory element or the conductive contact region connected to the memory element and (b) at least one second contact opening that exposes the TFR film layer comprises:
performing a first etch that stops at the first contact etch stop layer and the second contact etch stop layer; and
performing a second etch that extends through the first contact etch stop layer and second contact etch stop layer to expose the memory element or conductive contact region connected to the memory element, and the TFR film layer.
19. The method of claim 12 , comprising forming and annealing the TFR film layer prior to forming a first metal layer on the IC structure.