Selective dual silicide formation using a maskless fabrication process flow
A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.
1. A method of fabricating a semiconductor device, comprising:
selectively forming a first dielectric layer such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor, wherein the first type of transistor and the second type of transistor have different types of conductivity;
selectively forming a first silicide layer such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor;
forming a second dielectric layer over the first silicide layer, wherein the second dielectric layer and the first dielectric layer have different material compositions, and wherein the second dielectric layer is formed for one of, but not both, the first type of transistor and the second type of transistor;
removing the first dielectric layer after the second dielectric layer has been formed; and
forming a second silicide layer over the source/drain region of the first type of transistor.
2. The method of claim 1 , wherein:
the selectively forming the first dielectric layer comprises forming an oxide material as the first dielectric layer; and
the forming the second silicide layer comprises forming a nitride material as the second dielectric layer.
3. The method of claim 1 , wherein:
the first type of transistor includes a PFET;
the second type of transistor includes an NFET; and
the second dielectric layer is formed for the NFET but not for the PFET.
4. The method of claim 1 , wherein:
the first type of transistor includes a PFET;
the second type of transistor includes an NFET;
the selectively forming the first silicide layer comprises forming the first silicide layer having a first work function; and
the forming the second silicide layer comprises forming the second silicide layer having a second work function greater than the first work function.
5. The method of claim 1 , wherein:
the first type of transistor includes an NFET;
the second type of transistor includes a PFET;
the selectively forming the first silicide layer comprises forming the first silicide layer having a first work function; and
the forming the second silicide layer comprises forming the second silicide layer having a second work function less than the first work function.
6. The method of claim 1 , wherein the removing the first dielectric layer comprises etching a recess into the source/drain region of the first type of transistor.
7. The method of claim 1 , wherein the forming of the second silicide layer comprises directly depositing the second silicide layer over the source/drain region of the first type of transistor, and wherein the method further comprises: forming a first conductive contact over the first silicide layer and forming a second conductive contact over the second silicide layer.
8. The method of claim 1 , further comprising: before the forming the second silicide layer, forming a first conductive contact over the first silicide layer and forming a second conductive contact over the source/drain region of the first type of transistor, wherein the forming the second silicide layer comprises performing an annealing process to cause a reaction between the second conductive contact and the source/drain region of the first type of transistor, thereby forming the second silicide layer.
9. A method of fabricating a semiconductor device, comprising:
forming a first dielectric layer over a source/drain region of a first transistor but not over a source/drain region of a second transistor, wherein one of the first transistor and the second transistor is a PFET, and the other one of the first transistor and the second transistor is an NFET;
forming a first silicide layer over the source/drain region of the second transistor but not over the source/drain region of the first transistor;
forming a second dielectric layer over the first silicide layer, wherein the first dielectric layer and the second dielectric layer have different material compositions, and wherein the second dielectric layer is formed for one of, but not both, the first transistor and the second transistor;
removing the first dielectric layer after the first silicide layer and the second dielectric layer are formed; and
forming a second silicide layer over the source/drain region of the first transistor after the first dielectric layer is removed.
10. The method of claim 9 , wherein:
the selectively forming the first silicide layer comprises forming the first silicide layer having a first work function; and
the forming the second silicide layer comprises forming the second silicide layer having a second work function greater than or less than the first work function.
11. The method of claim 9 , wherein the removing the first dielectric layer comprises etching a recess into the source/drain region of the first transistor.
12. The method of claim 9 , wherein the forming of the second silicide layer comprises directly depositing the second silicide layer over the source/drain region of the first transistor, and wherein the method further comprises: forming a first conductive contact over the first silicide layer and forming a second conductive contact over the second silicide layer.
13. The method of claim 9 , further comprising: before the forming the second silicide layer, forming a first conductive contact over the first silicide layer and forming a second conductive contact over the source/drain region of the first transistor, wherein the forming the second silicide layer comprises performing an annealing process to cause a reaction between the second conductive contact and the source/drain region of the first transistor, thereby forming the second silicide layer.
14. A method of fabricating a semiconductor device, comprising:
forming a first dielectric layer over a source/drain region of a first transistor but not over a source/drain region of a second transistor, wherein one of the first transistor and the second transistor is a PFET, and the other one of the first transistor and the second transistor is an NFET;
forming a first silicide layer over the source/drain region of the second transistor but not over the source/drain region of the first transistor, wherein the first silicide layer is associated with a first work function;
forming a second dielectric layer over the first silicide layer, wherein the first dielectric layer and the second dielectric layer have different material compositions, and wherein the second dielectric layer is formed in the NFET but not in the PFET;
after the forming the second dielectric layer, removing the first dielectric layer at least in part by etching a recess into the source/drain region of the first transistor; and
forming a second silicide layer over the source/drain region of the first transistor, wherein the second silicide layer is associated with a second work function that is different from the first work function.
15. The method of claim 14 , wherein the first transistor is the PFET, and wherein the second transistor is the NFET.
16. The method of claim 14 , wherein the first dielectric layer contains oxide, and wherein the second dielectric layer contains nitride.
17. The method of claim 14 , wherein the first silicide layer and the second silicide layer are formed to have different work functions.
18. The method of claim 14 , further comprising: after the first dielectric layer has been formed, growing an epi-layer over the source/drain region of the second transistor, wherein the first silicide layer is formed on the epi-layer.
19. The method of claim 1 , further comprising: after the first dielectric layer has been formed, growing an epi-layer over the source/drain region of the second type of transistor, wherein the first silicide layer is formed on the epi-layer.
20. The method of claim 9 , further comprising: after the first dielectric layer has been formed, growing an epi-layer over the source/drain region of the NFET, wherein the first silicide layer is formed on the epi-layer.