Semiconductor device
A semiconductor device may include first and second active regions on a substrate, first and second active patterns on the first and second active regions, first and second source/drain patterns on the first and second active patterns, first and second silicide patterns on the first and second source/drain patterns, and first and second active contacts coupled to the first and second source/drain patterns. A lowermost portion of the first active contact is at a level higher than that of a lowermost portion of the second active contact. A thickness of the first silicide pattern is greater than that of the second silicide pattern.
1. A semiconductor device, comprising:
a substrate including a first active region and a second active region;
a first active pattern and a second active pattern on the first active region and the second active region, respectively;
a first source/drain pattern and a second source/drain pattern on the first active pattern and the second active pattern, respectively;
a first silicide pattern and a second silicide pattern on the first source/drain pattern and the second source/drain pattern, respectively, a first thickness of the first silicide pattern being greater than a second thickness of the second silicide pattern; and
a first active contact and a second active contact coupled to the first source/drain pattern and the second active pattern, respectively, a lowermost portion of the first active contact being at a higher level than a lowermost portion of the second active contact,
wherein a low onion of the first silicide pattern is at a lower level than an uppermost portion of the first active pattern.
2. The semiconductor device as claimed in claim 1 , wherein the first active region is a PMOSFET region, and the second active region is an NMOSFET region.
3. The semiconductor device as claimed in claim 1 , wherein a third thickness of the first source/drain pattern is greater than a fourth thickness of the second source/drain pattern.
4. The semiconductor device as claimed in claim 1 , further comprising a first recess and a second recess on an upper portion of the first active pattern and an upper portion of the second active pattern, respectively, the first source/drain pattern and the first silicide pattern completely filling the first recess, and the second source/drain pattern and the second silicide pattern partially filling the second recess.
5. The semiconductor device as claimed in claim 4 , wherein the second active contact includes:
an extension part that extends into the second recess to contact an inner sidewall of the second silicide pattern; and
a body part on the extension part.
6. The semiconductor device as claimed in claim 5 , wherein a width of the extension part is less than a width of the body part.
7. The semiconductor device as claimed in claim 1 , further comprising a channel pattern connected to one of the first source/drain pattern and the second source/drain pattern, the channel pattern including stacked semiconductor patterns that are spaced apart from each other, and a bottom surface of a lowermost one of the stacked semiconductor patterns is at a higher level than a lowermost portion of the first silicide pattern.
8. The semiconductor device as claimed in claim 7 , wherein the bottom surface of the lowermost one of the stacked semiconductor patterns is at a higher level than a lowermost portion of the second silicide pattern.
9. The semiconductor device as claimed in claim 1 , wherein:
the lowermost portion of the first active contact is at a substantially same level as an uppermost surface of the first silicide pattern, and
the lowermost portion of the second active contact is at a level lower than an uppermost surface of the second silicide pattern.
10. The semiconductor device as claimed in claim 1 , wherein each of the first active contact and the second active contact includes:
a conductive pattern; and
a barrier pattern that covers a sidewall of the conductive pattern, the barrier pattern of the second active contact including a step part that covers at least a portion of a top surface of the second silicide pattern.
11. A semiconductor device, comprising:
a substrate including a first active pattern and a second active pattern, the first active pattern and the second active pattern being adjacent to each other in a first direction;
a gate electrode that extends in the first direction and crosses the first active pattern and the second active pattern;
a first recess and a second recess that are on an upper portion of the first active pattern and an upper portion of the second active pattern, respectively;
a first source/drain pattern and a second source/drain pattern that fill a portion of the first recess and a portion of the second recess, respectively;
a first active contact and a second active contact that are coupled to the first source/drain pattern and the second active pattern, respectively;
a first silicide pattern between the first source/drain pattern and the first active contact, the first active contact being in contact with a top surface of the first silicide pattern; and
a second silicide pattern between the second source/drain pattern and the second active contact, the second active contact including a first extension part that extends into the second recess to contact an inner sidewall of the second silicide pattern.
12. The semiconductor device as claimed in claim 11 , wherein:
a first thickness of the first silicide pattern is greater than a second thickness of the second silicide pattern, and
a third thickness of the first source/drain pattern is greater than a fourth thickness of the second source/drain pattern.
13. The semiconductor device as claimed in claim 11 , wherein a lowermost portion of the first active contact is at a higher level than a lowermost portion of the second active contact.
14. The semiconductor device as claimed in claim 11 , wherein the first active contact includes a second extension part that extends into the first recess.
15. The semiconductor device as claimed in claim 11 , wherein:
the first source/drain pattern has a p-type conductivity type, and
the second source/drain pattern has an n-type conductivity type.
16. A semiconductor device, comprising:
a substrate including a first active region and a second active region that are adjacent to each other in a first direction;
a first active pattern and a second active pattern that are on the first active region and the second active region, respectively;
a first source/drain pattern on the first active pattern and a second source/drain pattern on the second active pattern;
a first silicide pattern on the first source/drain pattern and a second silicide pattern on the second source/drain pattern;
a first channel pattern connected to the first source/drain pattern and a second channel pattern connected to the second source/drain pattern, each of the first channel pattern and the second channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern that are sequentially stacked and spaced apart from each other;
a gate electrode that extends in the first direction and crosses the first channel pattern and the second channel pattern, the gate electrode including a first part between the substrate and the first semiconductor pattern, a second part between the first semiconductor pattern and the second semiconductor pattern, a third part between the second semiconductor pattern and the third semiconductor pattern, and a fourth part on the third semiconductor pattern;
a gate dielectric layer between the first channel pattern and the gate electrode, and between the second channel pattern and the gate electrode;
a gate spacer on sidewalls of the gate electrode;
a gate capping pattern on a top surface of the gate electrode;
a first interlayer dielectric layer on the gate capping pattern;
a first active contact and a second active contact that penetrate the first interlayer dielectric layer and are respectively coupled to the first source/drain pattern and the second source/drain pattern;
a gate contact that penetrates the first interlayer dielectric layer and is coupled to the gate electrode;
a second interlayer dielectric layer on the first interlayer dielectric layer;
a first metal layer in the second interlayer dielectric layer, the first metal layer including a plurality of lower lines that are correspondingly electrically connected to the gate contact and the first active contact and the second active contact;
a third interlayer dielectric layer on the second interlayer dielectric layer; and
a second metal layer in the third interlayer dielectric layer,
wherein the second metal layer includes a plurality of upper lines that are correspondingly electrically connected to the plurality of lower lines,
wherein a lowermost portion of the first active contact is at a higher level than a lowermost portion of the second active contact, and
wherein a first thickness of the first silicide pattern is greater than a second thickness of the second silicide pattern.
17. The semiconductor device as claimed in claim 16 , wherein a bottom surface of the first semiconductor pattern is at a higher level than a lowermost portion of the first silicide pattern.
18. The semiconductor device as claimed in claim 16 , further comprising a first recess and a second recess that are on an upper portion of the first active pattern and an upper portion of the second active pattern, respectively, the first source/drain pattern and the first silicide pattern completely filling the first recess, and the second source/drain pattern and the second silicide pattern partially filling the second recess.
19. The semiconductor device as claimed in claim 18 , wherein the second active contact includes an extension part that extends into the second recess to contact an inner sidewall of the second silicide pattern.
20. The semiconductor device as claimed in claim 16 , wherein the first source/drain pattern includes silicon-germanium, and the second source/drain pattern includes silicon.