Decoding system and physical layout for analog neural memory in deep learning artificial neural network
Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.
1. An analog neural memory system comprising:
a vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a bit line terminal, a source line terminal, a word line terminal, and a floating gate adjacent to the word line terminal;
a plurality of bit lines, wherein each of the plurality of bit lines is coupled to the bit line terminals of a column of memory cells;
a plurality of word lines, wherein each of the plurality of word lines is coupled to the word line terminals of a column of memory cells; and
a plurality of source lines, wherein each of the plurality of source lines is coupled to the source line terminals of one or more rows of memory cells;
wherein the plurality of word lines are parallel to the plurality of bit lines and perpendicular to the plurality of source lines and, during a neuron read operation, an output is provided on the plurality of source lines that equals the sum of products generated for each cell in the array, wherein each product is equal to an input current received on a word line terminal of a cell multiplied by a weight stored in the cell.
2. The system of claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells.
3. The system of claim 1 , wherein the non-volatile memory cells are stacked-gate flash memory cells.
4. An analog neural memory system comprising:
a vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a bit line terminal, a source line terminal, a word line terminal, and a floating gate adjacent to the word line terminal;
a plurality of bit lines, wherein each of the plurality of bit lines is coupled to the bit line terminals of a column of memory cells;
a plurality of word lines, wherein each of the plurality of word lines is coupled to the word line terminals of a column of memory cells through one or more routing blocks; and
a plurality of source lines, wherein each of the plurality of source lines is coupled to the source line terminals of two rows of memory cells;
wherein the plurality of word lines are parallel to the plurality of bit lines and perpendicular to the plurality of source lines and, during a neuron read operation, an output is provided on the plurality of source lines that equals the sum of products generated for each cell in the array, wherein each product is equal to an input current received on a word line terminal of a cell multiplied by a weight stored in the cell; and
wherein the one or more routing blocks couple the plurality of word lines to the word line terminals of a row of memory cells, where the row is arranged in a direction perpendicular to the plurality of word lines.
5. The system of claim 4 , wherein the non-volatile memory cells are split-gate flash memory cells.
6. The system of claim 4 , wherein the non-volatile memory cells are stacked-gate flash memory cells.